diff options
Diffstat (limited to 'platforms/chibios/boards')
27 files changed, 1624 insertions, 126 deletions
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/mcuconf.h b/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/mcuconf.h index ba6e934fe7..a21fd7bd12 100644 --- a/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/mcuconf.h +++ b/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -32,11 +32,15 @@ */ #define STM32F4xx_MCUCONF +#define STM32F401_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE @@ -44,13 +48,13 @@ #define STM32_CLOCK48_REQUIRED TRUE #define STM32_SW STM32_SW_PLL #define STM32_PLLSRC STM32_PLLSRC_HSE -#define STM32_PLLM_VALUE 25 -#define STM32_PLLN_VALUE 336 -#define STM32_PLLP_VALUE 4 -#define STM32_PLLQ_VALUE 7 -#define STM32_HPRE STM32_HPRE_DIV1 -#define STM32_PPRE1 STM32_PPRE1_DIV4 -#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 #define STM32_RTCSEL STM32_RTCSEL_LSI #define STM32_RTCPRE_VALUE 8 #define STM32_MCO1SEL STM32_MCO1SEL_HSI @@ -60,9 +64,6 @@ #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE /* * IRQ system settings. @@ -82,6 +83,19 @@ #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 + /* * ADC driver system settings. */ @@ -101,14 +115,8 @@ #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE #define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -155,29 +163,20 @@ #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE /* * SERIAL driver system settings. @@ -185,9 +184,6 @@ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. @@ -227,9 +223,6 @@ #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 @@ -241,9 +234,7 @@ #define STM32_USB_USE_OTG1 TRUE #define STM32_USB_OTG1_IRQ_PRIORITY 14 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1 -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 +#define STM32_USB_HOST_WAKEUP_DURATION 2 /* * WDG driver system settings. diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/mcuconf.h b/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/mcuconf.h index 0394ff56bb..131c847661 100644 --- a/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/mcuconf.h +++ b/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -32,11 +32,15 @@ */ #define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED TRUE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE @@ -60,9 +64,6 @@ #define STM32_I2SSRC STM32_I2SSRC_CKIN #define STM32_PLLI2SN_VALUE 192 #define STM32_PLLI2SR_VALUE 5 -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE /* * IRQ system settings. @@ -82,6 +83,19 @@ #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 + /* * ADC driver system settings. */ @@ -101,14 +115,8 @@ #define STM32_GPT_USE_TIM4 FALSE #define STM32_GPT_USE_TIM5 FALSE #define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE #define STM32_GPT_USE_TIM11 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -155,29 +163,28 @@ #define STM32_ICU_USE_TIM4 FALSE #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 /* * SERIAL driver system settings. @@ -185,9 +192,6 @@ #define STM32_SERIAL_USE_USART1 FALSE #define STM32_SERIAL_USE_USART2 FALSE #define STM32_SERIAL_USE_USART6 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 /* * SPI driver system settings. @@ -227,9 +231,6 @@ #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART6_DMA_PRIORITY 0 @@ -241,9 +242,7 @@ #define STM32_USB_USE_OTG1 TRUE #define STM32_USB_OTG1_IRQ_PRIORITY 14 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 -#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1 -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 +#define STM32_USB_HOST_WAKEUP_DURATION 2 /* * WDG driver system settings. diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk new file mode 100644 index 0000000000..6c837bb8ee --- /dev/null +++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC)
\ No newline at end of file diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h new file mode 100644 index 0000000000..8cb771bc12 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/board.h @@ -0,0 +1,28 @@ +/* Copyright 2020 Nick Brassel (tzarc) + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#define STM32_HSECLK 12000000 +// The following is required to disable the pull-down on PA9, when PA9 is used for the keyboard matrix: +#define BOARD_OTG_NOVBUSSENS + +#include_next "board.h" + +#undef STM32_HSE_BYPASS + +#undef STM32F407xx +#define STM32F405xG +#define STM32F405xx diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h new file mode 100644 index 0000000000..cc52a953ed --- /dev/null +++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h @@ -0,0 +1,23 @@ +/* Copyright 2021 Andrei Purdea + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Address for jumping to bootloader on STM32 chips. */ +/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606. + */ +#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000 +#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP +# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE +#endif diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h new file mode 100644 index 0000000000..908a580a91 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/mcuconf.h @@ -0,0 +1,352 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F405_MCUCONF +#define STM32F415_MCUCONF +#define STM32F407_MCUCONF +#define STM32F417_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 12 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 1000 +#define STM32_SDC_READ_TIMEOUT_MS 1000 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_HOST_WAKEUP_DURATION 2 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h index 4be47fe1b0..928ee56c71 100644 --- a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h +++ b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/mcuconf.h @@ -344,9 +344,6 @@ #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 #define STM32_USB_HOST_WAKEUP_DURATION 2 -#define STM32_USB_OTG_THREAD_PRIO NORMALPRIO+1 -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 - /* * WDG driver system settings. */ diff --git a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h index d2de75590e..566c146c25 100644 --- a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h +++ b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/mcuconf.h @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -32,11 +32,15 @@ */ #define STM32F4xx_MCUCONF +#define STM32F446_MCUCONF /* * HAL driver system settings. */ #define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE #define STM32_HSI_ENABLED FALSE #define STM32_LSI_ENABLED TRUE #define STM32_HSE_ENABLED TRUE @@ -70,9 +74,6 @@ #define STM32_SAI1SEL STM32_SAI2SEL_PLLR #define STM32_SAI2SEL STM32_SAI2SEL_PLLR #define STM32_CK48MSEL STM32_CK48MSEL_PLLALT -#define STM32_PVD_ENABLE FALSE -#define STM32_PLS STM32_PLS_LEV0 -#define STM32_BKPRAM_ENABLE FALSE /* * IRQ system settings. @@ -92,6 +93,30 @@ #define STM32_IRQ_EXTI21_PRIORITY 15 #define STM32_IRQ_EXTI22_PRIORITY 15 +#define STM32_IRQ_TIM1_BRK_TIM9_PRIORITY 7 +#define STM32_IRQ_TIM1_UP_TIM10_PRIORITY 7 +#define STM32_IRQ_TIM1_TRGCO_TIM11_PRIORITY 7 +#define STM32_IRQ_TIM1_CC_PRIORITY 7 +#define STM32_IRQ_TIM2_PRIORITY 7 +#define STM32_IRQ_TIM3_PRIORITY 7 +#define STM32_IRQ_TIM4_PRIORITY 7 +#define STM32_IRQ_TIM5_PRIORITY 7 +#define STM32_IRQ_TIM6_PRIORITY 7 +#define STM32_IRQ_TIM7_PRIORITY 7 +#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7 +#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7 +#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7 +#define STM32_IRQ_TIM8_CC_PRIORITY 7 + +#define STM32_IRQ_USART1_PRIORITY 12 +#define STM32_IRQ_USART2_PRIORITY 12 +#define STM32_IRQ_USART3_PRIORITY 12 +#define STM32_IRQ_UART4_PRIORITY 12 +#define STM32_IRQ_UART5_PRIORITY 12 +#define STM32_IRQ_USART6_PRIORITY 12 +#define STM32_IRQ_UART7_PRIORITY 12 +#define STM32_IRQ_UART8_PRIORITY 12 + /* * ADC driver system settings. */ @@ -143,21 +168,11 @@ #define STM32_GPT_USE_TIM7 FALSE #define STM32_GPT_USE_TIM8 FALSE #define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM10 FALSE #define STM32_GPT_USE_TIM11 FALSE #define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM13 FALSE #define STM32_GPT_USE_TIM14 FALSE -#define STM32_GPT_TIM1_IRQ_PRIORITY 7 -#define STM32_GPT_TIM2_IRQ_PRIORITY 7 -#define STM32_GPT_TIM3_IRQ_PRIORITY 7 -#define STM32_GPT_TIM4_IRQ_PRIORITY 7 -#define STM32_GPT_TIM5_IRQ_PRIORITY 7 -#define STM32_GPT_TIM6_IRQ_PRIORITY 7 -#define STM32_GPT_TIM7_IRQ_PRIORITY 7 -#define STM32_GPT_TIM8_IRQ_PRIORITY 7 -#define STM32_GPT_TIM9_IRQ_PRIORITY 7 -#define STM32_GPT_TIM11_IRQ_PRIORITY 7 -#define STM32_GPT_TIM12_IRQ_PRIORITY 7 -#define STM32_GPT_TIM14_IRQ_PRIORITY 7 /* * I2C driver system settings. @@ -205,13 +220,11 @@ #define STM32_ICU_USE_TIM5 FALSE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_USE_TIM9 FALSE -#define STM32_ICU_TIM1_IRQ_PRIORITY 7 -#define STM32_ICU_TIM2_IRQ_PRIORITY 7 -#define STM32_ICU_TIM3_IRQ_PRIORITY 7 -#define STM32_ICU_TIM4_IRQ_PRIORITY 7 -#define STM32_ICU_TIM5_IRQ_PRIORITY 7 -#define STM32_ICU_TIM8_IRQ_PRIORITY 7 -#define STM32_ICU_TIM9_IRQ_PRIORITY 7 +#define STM32_ICU_USE_TIM10 FALSE +#define STM32_ICU_USE_TIM11 FALSE +#define STM32_ICU_USE_TIM12 FALSE +#define STM32_ICU_USE_TIM13 FALSE +#define STM32_ICU_USE_TIM14 FALSE /* * MAC driver system settings. @@ -227,7 +240,6 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE @@ -235,13 +247,19 @@ #define STM32_PWM_USE_TIM5 FALSE #define STM32_PWM_USE_TIM8 FALSE #define STM32_PWM_USE_TIM9 FALSE -#define STM32_PWM_TIM1_IRQ_PRIORITY 7 -#define STM32_PWM_TIM2_IRQ_PRIORITY 7 -#define STM32_PWM_TIM3_IRQ_PRIORITY 7 -#define STM32_PWM_TIM4_IRQ_PRIORITY 7 -#define STM32_PWM_TIM5_IRQ_PRIORITY 7 -#define STM32_PWM_TIM8_IRQ_PRIORITY 7 -#define STM32_PWM_TIM9_IRQ_PRIORITY 7 +#define STM32_PWM_USE_TIM10 FALSE +#define STM32_PWM_USE_TIM11 FALSE +#define STM32_PWM_USE_TIM12 FALSE +#define STM32_PWM_USE_TIM13 FALSE +#define STM32_PWM_USE_TIM14 FALSE + +/* + * RTC driver system settings. + */ +#define STM32_RTC_PRESA_VALUE 32 +#define STM32_RTC_PRESS_VALUE 1024 +#define STM32_RTC_CR_INIT 0 +#define STM32_RTC_TAMPCR_INIT 0 /* * SDC driver system settings. @@ -265,14 +283,6 @@ #define STM32_SERIAL_USE_USART6 FALSE #define STM32_SERIAL_USE_UART7 FALSE #define STM32_SERIAL_USE_UART8 FALSE -#define STM32_SERIAL_USART1_PRIORITY 12 -#define STM32_SERIAL_USART2_PRIORITY 12 -#define STM32_SERIAL_USART3_PRIORITY 12 -#define STM32_SERIAL_UART4_PRIORITY 12 -#define STM32_SERIAL_UART5_PRIORITY 12 -#define STM32_SERIAL_USART6_PRIORITY 12 -#define STM32_SERIAL_UART7_PRIORITY 12 -#define STM32_SERIAL_UART8_PRIORITY 12 /* * SPI driver system settings. @@ -281,6 +291,8 @@ #define STM32_SPI_USE_SPI2 FALSE #define STM32_SPI_USE_SPI3 FALSE #define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) @@ -289,14 +301,22 @@ #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) #define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 #define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 #define STM32_SPI_SPI1_IRQ_PRIORITY 10 #define STM32_SPI_SPI2_IRQ_PRIORITY 10 #define STM32_SPI_SPI3_IRQ_PRIORITY 10 #define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") /* @@ -326,12 +346,6 @@ #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_UART_USART1_IRQ_PRIORITY 12 -#define STM32_UART_USART2_IRQ_PRIORITY 12 -#define STM32_UART_USART3_IRQ_PRIORITY 12 -#define STM32_UART_UART4_IRQ_PRIORITY 12 -#define STM32_UART_UART5_IRQ_PRIORITY 12 -#define STM32_UART_USART6_IRQ_PRIORITY 12 #define STM32_UART_USART1_DMA_PRIORITY 0 #define STM32_UART_USART2_DMA_PRIORITY 0 #define STM32_UART_USART3_DMA_PRIORITY 0 @@ -349,9 +363,7 @@ #define STM32_USB_OTG2_IRQ_PRIORITY 14 #define STM32_USB_OTG1_RX_FIFO_SIZE 512 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024 -#define STM32_USB_OTG_THREAD_PRIO LOWPRIO -#define STM32_USB_OTG_THREAD_STACK_SIZE 128 -#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 +#define STM32_USB_HOST_WAKEUP_DURATION 2 /* * WDG driver system settings. diff --git a/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h index 182d4885d7..d115028300 100644 --- a/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h +++ b/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/mcuconf.h @@ -40,9 +40,24 @@ */ #define STM32_NO_INIT FALSE #define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PWR_BOOST TRUE #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) #define STM32_PWR_CR4 (0U) +#define STM32_PWR_PUCRA (0U) +#define STM32_PWR_PDCRA (0U) +#define STM32_PWR_PUCRB (0U) +#define STM32_PWR_PDCRB (0U) +#define STM32_PWR_PUCRC (0U) +#define STM32_PWR_PDCRC (0U) +#define STM32_PWR_PUCRD (0U) +#define STM32_PWR_PDCRD (0U) +#define STM32_PWR_PUCRE (0U) +#define STM32_PWR_PDCRE (0U) +#define STM32_PWR_PUCRF (0U) +#define STM32_PWR_PDCRF (0U) +#define STM32_PWR_PUCRG (0U) +#define STM32_PWR_PDCRG (0U) #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE #define STM32_HSE_ENABLED FALSE diff --git a/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h index 117e920e3b..5710e2cb45 100644 --- a/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h +++ b/platforms/chibios/boards/GENERIC_STM32_G474XE/configs/mcuconf.h @@ -42,9 +42,24 @@ */ #define STM32_NO_INIT FALSE #define STM32_VOS STM32_VOS_RANGE1 +#define STM32_PWR_BOOST TRUE #define STM32_PWR_CR2 (PWR_CR2_PLS_LEV0) #define STM32_PWR_CR3 (PWR_CR3_EIWF) #define STM32_PWR_CR4 (0U) +#define STM32_PWR_PUCRA (0U) +#define STM32_PWR_PDCRA (0U) +#define STM32_PWR_PUCRB (0U) +#define STM32_PWR_PDCRB (0U) +#define STM32_PWR_PUCRC (0U) +#define STM32_PWR_PDCRC (0U) +#define STM32_PWR_PUCRD (0U) +#define STM32_PWR_PDCRD (0U) +#define STM32_PWR_PUCRE (0U) +#define STM32_PWR_PDCRE (0U) +#define STM32_PWR_PUCRF (0U) +#define STM32_PWR_PDCRF (0U) +#define STM32_PWR_PUCRG (0U) +#define STM32_PWR_PDCRG (0U) #define STM32_HSI16_ENABLED TRUE #define STM32_HSI48_ENABLED TRUE #define STM32_HSE_ENABLED FALSE diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.c b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.c new file mode 100644 index 0000000000..e38a7e0054 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.c @@ -0,0 +1,82 @@ +/* + Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void wb32_gpio_init(void) { + +#if WB32_HAS_GPIOA + rccEnableAPB1(RCC_APB1ENR_GPIOAEN); +#endif + +#if WB32_HAS_GPIOB + rccEnableAPB1(RCC_APB1ENR_GPIOBEN); +#endif + +#if WB32_HAS_GPIOC + rccEnableAPB1(RCC_APB1ENR_GPIOCEN); +#endif + +#if WB32_HAS_GPIOD + rccEnableAPB1(RCC_APB1ENR_GPIODEN); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + wb32_clock_init(); + wb32_gpio_init(); +} +/** + * @brief Board-specific initialization code. + * @note You can add your board-specific code here. + */ +void boardInit(void) { + +} diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h new file mode 100644 index 0000000000..51dc84db94 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.h @@ -0,0 +1,56 @@ +#pragma once +/* + Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup board. + */ + +/* + * Board identifier. + */ +#define WB32F3G71x9 +#if !defined(WB32F3G71xx) + #define WB32F3G71xx +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.mk b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.mk new file mode 100644 index 0000000000..842e335905 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = $(BOARD_PATH)/board/board.c + +# Required include directories +BOARDINC = $(BOARD_PATH)/board + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h new file mode 100644 index 0000000000..c929d2ad03 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h @@ -0,0 +1,12 @@ +/* Address for jumping to bootloader on WB32 chips. */ +/* It is chip dependent, the correct number can be looked up here: + * http://www.westberrytech.com/down/mcu/data/WB32F3G71xx_rm.pdf + */ +#ifndef WB32_BOOTLOADER_ADDRESS +# undef STM32_BOOTLOADER_ADDRESS +# define WB32_BOOTLOADER_ADDRESS 0x1FFFE000 +# define STM32_BOOTLOADER_ADDRESS WB32_BOOTLOADER_ADDRESS +#else +# undef STM32_BOOTLOADER_ADDRESS +# define STM32_BOOTLOADER_ADDRESS WB32_BOOTLOADER_ADDRESS +#endif diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h new file mode 100644 index 0000000000..e4afddb6a5 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h @@ -0,0 +1,26 @@ +/* Copyright 2020 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* + * This file was auto-generated by: + * `qmk chibios-confmigrate -i platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/chconf.h -r platforms/chibios/boards/common/configs/chconf.h` + */ + +#pragma once + +#define CH_CFG_ST_TIMEDELTA 0 + +#include_next <chconf.h>
\ No newline at end of file diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/config.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/config.h new file mode 100644 index 0000000000..9fdc825669 --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/config.h @@ -0,0 +1,20 @@ +/* Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <https://www.gnu.org/licenses/>. + */ +#pragma once + +#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP +# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE +#endif diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/mcuconf.h new file mode 100644 index 0000000000..7c1fdaf57d --- /dev/null +++ b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/mcuconf.h @@ -0,0 +1,168 @@ +/* + Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define WB32F3G71xx_MCUCONF TRUE + +/* + * WB32F3G71 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + */ + +/** + * @name Internal clock sources + * @{ + */ +#define WB32_HSECLK 12000000 +#define WB32_LSECLK 32768 + +/* + * HAL driver system settings. + */ +#define WB32_NO_INIT FALSE +#define WB32_MHSI_ENABLED TRUE +#define WB32_FHSI_ENABLED FALSE +#define WB32_LSI_ENABLED FALSE +#define WB32_HSE_ENABLED TRUE +#define WB32_LSE_ENABLED FALSE +#define WB32_PLL_ENABLED TRUE +#define WB32_MAINCLKSRC WB32_MAINCLKSRC_PLL +#define WB32_PLLSRC WB32_PLLSRC_HSE +#define WB32_PLLDIV_VALUE 2 +#define WB32_PLLMUL_VALUE 12 //The allowed range is 12,16,20,24. +#define WB32_HPRE 1 +#define WB32_PPRE1 1 +#define WB32_PPRE2 1 +#define WB32_USBPRE WB32_USBPRE_DIV1P5 + +/* + * EXTI driver system settings. + */ +#define WB32_IRQ_EXTI0_PRIORITY 6 +#define WB32_IRQ_EXTI1_PRIORITY 6 +#define WB32_IRQ_EXTI2_PRIORITY 6 +#define WB32_IRQ_EXTI3_PRIORITY 6 +#define WB32_IRQ_EXTI4_PRIORITY 6 +#define WB32_IRQ_EXTI5_9_PRIORITY 6 +#define WB32_IRQ_EXTI10_15_PRIORITY 6 +#define WB32_IRQ_EXTI16_PRIORITY 6 +#define WB32_IRQ_EXTI17_PRIORITY 6 +#define WB32_IRQ_EXTI18_PRIORITY 6 +#define WB32_IRQ_EXTI19_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define WB32_TIM_MAX_CHANNELS 4 +#define WB32_GPT_USE_TIM1 FALSE +#define WB32_GPT_USE_TIM2 FALSE +#define WB32_GPT_USE_TIM3 FALSE +#define WB32_GPT_USE_TIM4 FALSE +#define WB32_GPT_TIM1_IRQ_PRIORITY 7 +#define WB32_GPT_TIM2_IRQ_PRIORITY 7 +#define WB32_GPT_TIM3_IRQ_PRIORITY 7 +#define WB32_GPT_TIM4_IRQ_PRIORITY 7 + +/* + * ICU driver system settings. + */ +#define WB32_ICU_USE_TIM1 FALSE +#define WB32_ICU_USE_TIM2 FALSE +#define WB32_ICU_USE_TIM3 FALSE +#define WB32_ICU_USE_TIM4 FALSE +#define WB32_ICU_TIM1_IRQ_PRIORITY 7 +#define WB32_ICU_TIM2_IRQ_PRIORITY 7 +#define WB32_ICU_TIM3_IRQ_PRIORITY 7 +#define WB32_ICU_TIM4_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define WB32_PWM_USE_ADVANCED FALSE +#define WB32_PWM_USE_TIM1 FALSE +#define WB32_PWM_USE_TIM2 FALSE +#define WB32_PWM_USE_TIM3 FALSE +#define WB32_PWM_USE_TIM4 FALSE +#define WB32_PWM_TIM1_IRQ_PRIORITY 7 +#define WB32_PWM_TIM2_IRQ_PRIORITY 7 +#define WB32_PWM_TIM3_IRQ_PRIORITY 7 +#define WB32_PWM_TIM4_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define WB32_I2C_USE_I2C1 FALSE +#define WB32_I2C_USE_I2C2 FALSE +#define WB32_I2C_BUSY_TIMEOUT 50 +#define WB32_I2C_I2C1_IRQ_PRIORITY 5 +#define WB32_I2C_I2C2_IRQ_PRIORITY 5 + +/* + * SERIAL driver system settings. + */ +#define WB32_SERIAL_USE_UART1 FALSE +#define WB32_SERIAL_USE_UART2 FALSE +#define WB32_SERIAL_USE_UART3 FALSE +#define WB32_SERIAL_USART1_PRIORITY 12 +#define WB32_SERIAL_USART2_PRIORITY 12 +#define WB32_SERIAL_USART3_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define WB32_SPI_USE_QSPI FALSE +#define WB32_SPI_USE_SPIM2 FALSE +#define WB32_SPI_USE_SPIS1 FALSE +#define WB32_SPI_USE_SPIS2 FALSE +#define WB32_SPI_QSPI_IRQ_PRIORITY 10 +#define WB32_SPI_SPIM2_IRQ_PRIORITY 10 +#define WB32_SPI_SPIS1_IRQ_PRIORITY 10 +#define WB32_SPI_SPIS2_IRQ_PRIORITY 10 + +/* + * ST driver system settings. + */ +#define WB32_ST_IRQ_PRIORITY 8 +#define WB32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define WB32_UART_USE_UART1 FALSE +#define WB32_UART_USE_UART2 FALSE +#define WB32_UART_USE_UART3 FALSE +#define WB32_UART_UART1_IRQ_PRIORITY 12 +#define WB32_UART_UART2_IRQ_PRIORITY 12 +#define WB32_UART_UART3_IRQ_PRIORITY 12 + +/* + * USB driver system settings. + */ +#define WB32_USB_USE_USB1 TRUE +#define WB32_USB_USB1_IRQ_PRIORITY 13 +#define WB32_USB_HOST_WAKEUP_DURATION 10 + + +#endif /* MCUCONF_H */ diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h b/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h index a1cbf68086..f812332960 100644 --- a/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h +++ b/platforms/chibios/boards/QMK_PROTON_C/configs/chconf.h @@ -40,7 +40,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/config.h b/platforms/chibios/boards/QMK_PROTON_C/configs/config.h index a73f0c0b47..fa1a73c354 100644 --- a/platforms/chibios/boards/QMK_PROTON_C/configs/config.h +++ b/platforms/chibios/boards/QMK_PROTON_C/configs/config.h @@ -18,3 +18,12 @@ #ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP # define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE #endif + +#ifdef CONVERT_TO_PROTON_C +# ifndef I2C1_SDA_PIN +# define I2C1_SDA_PIN D1 +# endif +# ifndef I2C1_SCL_PIN +# define I2C1_SCL_PIN D0 +# endif +#endif diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk b/platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk new file mode 100644 index 0000000000..960fc26786 --- /dev/null +++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/board/board.mk @@ -0,0 +1,9 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h new file mode 100644 index 0000000000..6e5adb0fe1 --- /dev/null +++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/chconf.h @@ -0,0 +1,23 @@ +/* Copyright 2021 QMK + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/* To compile the ChibiOS syscall stubs with picolibc + * the _reent struct has to be defined. */ +#if !defined(_FROM_ASM_) && defined(USE_PICOLIBC) +struct _reent; +#endif + +#include_next <chconf.h>
\ No newline at end of file diff --git a/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h new file mode 100644 index 0000000000..ab086567e5 --- /dev/null +++ b/platforms/chibios/boards/SIPEED_LONGAN_NANO/configs/mcuconf.h @@ -0,0 +1,302 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + ChibiOS - Copyright (C) 2021 Stefan Kerkmann + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#pragma once + +#define GD32VF103_MCUCONF +#define GD32VF103CB + +/* + * GD32VF103 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 0...15 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. +*/ + +#if defined(OVERCLOCK_120MHZ) +/* (8MHz / 2) * 30 = 120MHz Sysclock */ +#define GD32_ALLOW_120MHZ_SYSCLK +#define GD32_PLLMF_VALUE 30 +#define GD32_USBFSPSC GD32_USBFSPSC_DIV2P5 +#else +/* (8MHz / 2) * 24 = 96MHz Sysclock */ +#define GD32_PLLMF_VALUE 24 +#define GD32_USBFSPSC GD32_USBFSPSC_DIV2 +#endif + +#define GD32_NO_INIT FALSE +#define GD32_IRC8M_ENABLED TRUE +#define GD32_IRC40K_ENABLED FALSE +#define GD32_HXTAL_ENABLED TRUE +#define GD32_LXTAL_ENABLED FALSE +#define GD32_SCS GD32_SCS_PLL +#define GD32_PLLSEL GD32_PLLSEL_PREDV0 +#define GD32_PREDV0SEL GD32_PREDV0SEL_HXTAL +#define GD32_PREDV0_VALUE 2 +#define GD32_PREDV1_VALUE 2 +#define GD32_PLL1MF_VALUE 14 +#define GD32_PLL2MF_VALUE 13 +#define GD32_AHBPSC GD32_AHBPSC_DIV1 +#define GD32_APB1PSC GD32_APB1PSC_DIV2 +#define GD32_APB2PSC GD32_APB2PSC_DIV1 +#define GD32_ADCPSC GD32_ADCPSC_DIV16 +#define GD32_USB_CLOCK_REQUIRED TRUE +#define GD32_I2S_CLOCK_REQUIRED FALSE +#define GD32_CKOUT0SEL GD32_CKOUT0SEL_NOCLOCK +#define GD32_RTCSRC GD32_RTCSRC_NOCLOCK +#define GD32_PVD_ENABLE FALSE +#define GD32_LVDT GD32_LVDT_LEV0 + +/* + * ECLIC system settings. + */ +#define ECLIC_TRIGGER_DEFAULT ECLIC_POSTIVE_EDGE_TRIGGER +#define ECLIC_DMA_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * IRQ system settings. + */ +#define GD32_IRQ_EXTI0_PRIORITY 6 +#define GD32_IRQ_EXTI1_PRIORITY 6 +#define GD32_IRQ_EXTI2_PRIORITY 6 +#define GD32_IRQ_EXTI3_PRIORITY 6 +#define GD32_IRQ_EXTI4_PRIORITY 6 +#define GD32_IRQ_EXTI5_9_PRIORITY 6 +#define GD32_IRQ_EXTI10_15_PRIORITY 6 +#define GD32_IRQ_EXTI0_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_IRQ_EXTI1_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_IRQ_EXTI2_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_IRQ_EXTI3_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_IRQ_EXTI4_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_IRQ_EXTI5_9_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_IRQ_EXTI10_15_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * ADC driver system settings. + */ +#define GD32_ADC_USE_ADC0 FALSE +#define GD32_ADC_ADC0_DMA_PRIORITY 2 +#define GD32_ADC_ADC0_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define GD32_CAN_USE_CAN0 FALSE +#define GD32_CAN_CAN0_IRQ_PRIORITY 11 +#define GD32_CAN_USE_CAN1 FALSE +#define GD32_CAN_CAN1_IRQ_PRIORITY 11 +#define GD32_CAN_CAN0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_CAN_CAN1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * CRC driver system settings. + */ +#define GD32_CRC_USE_CRC0 FALSE +#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY 14 +#define GD32_CRC_CRC0_DMA_PRIORITY 2 +#define GD32_CRC_CRC0_DMA_STREAM GD32_DMA_STREAM_ID(0, 0) +#define CRC_USE_DMA FALSE +#define CRCSW_USE_CRC1 FALSE +#define CRCSW_CRC32_TABLE FALSE +#define CRCSW_CRC16_TABLE FALSE +#define CRCSW_PROGRAMMABLE FALSE + +/* + * DAC driver system settings. + */ +#define GD32_DAC_USE_DAC_CH1 FALSE +#define GD32_DAC_USE_DAC_CH2 FALSE + +/* + * GPT driver system settings. + */ +#define GD32_GPT_USE_TIM0 FALSE +#define GD32_GPT_USE_TIM1 FALSE +#define GD32_GPT_USE_TIM2 FALSE +#define GD32_GPT_USE_TIM3 FALSE +#define GD32_GPT_USE_TIM4 FALSE +#define GD32_GPT_TIM0_IRQ_PRIORITY 7 +#define GD32_GPT_TIM1_IRQ_PRIORITY 7 +#define GD32_GPT_TIM2_IRQ_PRIORITY 7 +#define GD32_GPT_TIM3_IRQ_PRIORITY 7 +#define GD32_GPT_TIM4_IRQ_PRIORITY 7 +#define GD32_GPT_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_GPT_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_GPT_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_GPT_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_GPT_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_GPT_TIM5_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_GPT_TIM6_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * I2S driver system settings. + */ +#define GD32_I2S_USE_SPI1 FALSE +#define GD32_I2S_USE_SPI2 FALSE +#define GD32_I2S_SPI1_IRQ_PRIORITY 10 +#define GD32_I2S_SPI2_IRQ_PRIORITY 10 +#define GD32_I2S_SPI1_DMA_PRIORITY 1 +#define GD32_I2S_SPI2_DMA_PRIORITY 1 +#define GD32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * I2C driver system settings. + */ +#define GD32_I2C_USE_I2C0 FALSE +#define GD32_I2C_USE_I2C1 FALSE +#define GD32_I2C_BUSY_TIMEOUT 50 +#define GD32_I2C_I2C0_IRQ_PRIORITY 10 +#define GD32_I2C_I2C1_IRQ_PRIORITY 5 +#define GD32_I2C_I2C0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_I2C_I2C1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_I2C_I2C0_DMA_PRIORITY 2 +#define GD32_I2C_I2C1_DMA_PRIORITY 2 +#define GD32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define GD32_ICU_USE_TIM0 FALSE +#define GD32_ICU_USE_TIM1 FALSE +#define GD32_ICU_USE_TIM2 FALSE +#define GD32_ICU_USE_TIM3 FALSE +#define GD32_ICU_USE_TIM4 FALSE +#define GD32_ICU_TIM0_IRQ_PRIORITY 7 +#define GD32_ICU_TIM1_IRQ_PRIORITY 7 +#define GD32_ICU_TIM2_IRQ_PRIORITY 7 +#define GD32_ICU_TIM3_IRQ_PRIORITY 7 +#define GD32_ICU_TIM4_IRQ_PRIORITY 7 +#define GD32_ICU_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_ICU_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_ICU_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_ICU_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_ICU_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * PWM driver system settings. + */ +#define GD32_PWM_USE_ADVANCED FALSE +#define GD32_PWM_USE_TIM0 FALSE +#define GD32_PWM_USE_TIM1 FALSE +#define GD32_PWM_USE_TIM2 FALSE +#define GD32_PWM_USE_TIM3 FALSE +#define GD32_PWM_USE_TIM4 FALSE +#define GD32_PWM_TIM0_IRQ_PRIORITY 10 +#define GD32_PWM_TIM1_IRQ_PRIORITY 10 +#define GD32_PWM_TIM2_IRQ_PRIORITY 10 +#define GD32_PWM_TIM3_IRQ_PRIORITY 10 +#define GD32_PWM_TIM4_IRQ_PRIORITY 10 +#define GD32_PWM_TIM0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_PWM_TIM1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_PWM_TIM2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_PWM_TIM3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_PWM_TIM4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * RTC driver system settings. + */ +#define GD32_RTC_IRQ_PRIORITY 15 +#define GD32_RTC_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * SERIAL driver system settings. + */ +#define GD32_SERIAL_USE_USART0 FALSE +#define GD32_SERIAL_USE_USART1 FALSE +#define GD32_SERIAL_USE_USART2 FALSE +#define GD32_SERIAL_USE_UART3 FALSE +#define GD32_SERIAL_USE_UART4 FALSE +#define GD32_SERIAL_USART0_PRIORITY 10 +#define GD32_SERIAL_USART1_PRIORITY 10 +#define GD32_SERIAL_USART2_PRIORITY 10 +#define GD32_SERIAL_UART3_PRIORITY 10 +#define GD32_SERIAL_UART4_PRIORITY 10 +#define GD32_SERIAL_USART0_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_SERIAL_USART1_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_SERIAL_USART2_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_SERIAL_UART3_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_SERIAL_UART4_TRIGGER ECLIC_TRIGGER_DEFAULT + +/* + * SPI driver system settings. + */ +#define GD32_SPI_USE_SPI0 FALSE +#define GD32_SPI_USE_SPI1 FALSE +#define GD32_SPI_USE_SPI2 FALSE +#define GD32_SPI_SPI0_DMA_PRIORITY 1 +#define GD32_SPI_SPI1_DMA_PRIORITY 1 +#define GD32_SPI_SPI2_DMA_PRIORITY 1 +#define GD32_SPI_SPI0_IRQ_PRIORITY 10 +#define GD32_SPI_SPI1_IRQ_PRIORITY 10 +#define GD32_SPI_SPI2_IRQ_PRIORITY 10 +#define GD32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define GD32_ST_IRQ_PRIORITY 10 +#define GD32_ST_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_ST_USE_TIMER 1 + +/* + * UART driver system settings. + */ +#define GD32_UART_USE_USART0 FALSE +#define GD32_UART_USE_USART1 FALSE +#define GD32_UART_USE_USART2 FALSE +#define GD32_UART_USE_UART3 FALSE +#define GD32_UART_USE_UART4 FALSE +#define GD32_UART_USART0_IRQ_PRIORITY 10 +#define GD32_UART_USART1_IRQ_PRIORITY 10 +#define GD32_UART_USART2_IRQ_PRIORITY 10 +#define GD32_UART_UART3_IRQ_PRIORITY 10 +#define GD32_UART_UART4_IRQ_PRIORITY 10 +#define GD32_UART_USART0_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_UART_USART1_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_UART_USART2_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_UART_UART3_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_UART_UART4_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_UART_USART0_DMA_PRIORITY 3 +#define GD32_UART_USART1_DMA_PRIORITY 3 +#define GD32_UART_USART2_DMA_PRIORITY 3 +#define GD32_UART_UART3_DMA_PRIORITY 3 +#define GD32_UART_UART4_DMA_PRIORITY 3 +#define GD32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define GD32_USB_USE_USBFS TRUE +#define GD32_USB_USBFS_IRQ_PRIORITY 10 +#define GD32_USB_USBFS_IRQ_TRIGGER ECLIC_TRIGGER_DEFAULT +#define GD32_USB_USBFS_RX_FIFO_SIZE 256 + +/* + * WDG driver system settings. + */ +#define GD32_WDG_USE_FWDGT FALSE diff --git a/platforms/chibios/boards/common/configs/chconf.h b/platforms/chibios/boards/common/configs/chconf.h index 44327a82d7..18ad609ca1 100644 --- a/platforms/chibios/boards/common/configs/chconf.h +++ b/platforms/chibios/boards/common/configs/chconf.h @@ -40,7 +40,7 @@ /** * @brief System time counter resolution. - * @note Allowed values are 16 or 32 bits. + * @note Allowed values are 16, 32 or 64 bits. */ #if !defined(CH_CFG_ST_RESOLUTION) #define CH_CFG_ST_RESOLUTION 32 diff --git a/platforms/chibios/boards/common/ld/STM32F401xC.ld b/platforms/chibios/boards/common/ld/STM32F401xC.ld new file mode 100644 index 0000000000..8fae66cec9 --- /dev/null +++ b/platforms/chibios/boards/common/ld/STM32F401xC.ld @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F401xC memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */ + flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */ + flash2 (rx) : org = 0x08008000, len = 256k - 32k /* Sector 2..6 - Rest of firmware */ + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 64k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash2); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/platforms/chibios/boards/common/ld/STM32F401xE.ld b/platforms/chibios/boards/common/ld/STM32F401xE.ld new file mode 100644 index 0000000000..69af7ed71e --- /dev/null +++ b/platforms/chibios/boards/common/ld/STM32F401xE.ld @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F401xE memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */ + flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */ + flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */ + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 96k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash2); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/platforms/chibios/boards/common/ld/STM32F405xG.ld b/platforms/chibios/boards/common/ld/STM32F405xG.ld new file mode 100644 index 0000000000..b7d0baa210 --- /dev/null +++ b/platforms/chibios/boards/common/ld/STM32F405xG.ld @@ -0,0 +1,86 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F405xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */ + flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */ + flash2 (rx) : org = 0x08008000, len = 1M - 32k /* Sector 2..6 - Rest of firmware */ + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 (wx) : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 (wx) : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 (wx) : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash2); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/platforms/chibios/boards/common/ld/STM32F411xE.ld b/platforms/chibios/boards/common/ld/STM32F411xE.ld new file mode 100644 index 0000000000..aea8084b51 --- /dev/null +++ b/platforms/chibios/boards/common/ld/STM32F411xE.ld @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F411xE memory setup. + */ +MEMORY +{ + flash0 (rx) : org = 0x08000000, len = 16k /* Sector 0 - Init code as ROM bootloader assumes application starts here */ + flash1 (rx) : org = 0x08004000, len = 16k /* Sector 1 - Emulated eeprom */ + flash2 (rx) : org = 0x08008000, len = 512k - 32k /* Sector 2..7 - Rest of firmware */ + flash3 (rx) : org = 0x00000000, len = 0 + flash4 (rx) : org = 0x00000000, len = 0 + flash5 (rx) : org = 0x00000000, len = 0 + flash6 (rx) : org = 0x00000000, len = 0 + flash7 (rx) : org = 0x00000000, len = 0 + ram0 (wx) : org = 0x20000000, len = 128k + ram1 (wx) : org = 0x00000000, len = 0 + ram2 (wx) : org = 0x00000000, len = 0 + ram3 (wx) : org = 0x00000000, len = 0 + ram4 (wx) : org = 0x00000000, len = 0 + ram5 (wx) : org = 0x00000000, len = 0 + ram6 (wx) : org = 0x00000000, len = 0 + ram7 (wx) : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash2); +REGION_ALIAS("XTORS_FLASH_LMA", flash2); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash2); +REGION_ALIAS("TEXT_FLASH_LMA", flash2); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash2); +REGION_ALIAS("RODATA_FLASH_LMA", flash2); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash2); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash2); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash2); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld |