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authorJoel Challis <git@zvecr.com>2021-03-10 22:47:36 +0000
committerGitHub <noreply@github.com>2021-03-10 22:47:36 +0000
commit40c7ecfdeaf50ab76e10854a84aebfcb82ddb092 (patch)
tree035c7d9a905198bdab9a659e653da6d320e1708b /quantum
parent2e24cfadb75b00156acf2827d5643d6c2d55a60c (diff)
Move gpio wait logic to wait.h (#12067)
Diffstat (limited to 'quantum')
-rw-r--r--quantum/quantum.h33
1 files changed, 0 insertions, 33 deletions
diff --git a/quantum/quantum.h b/quantum/quantum.h
index 7c2dcaa829..7c546b5152 100644
--- a/quantum/quantum.h
+++ b/quantum/quantum.h
@@ -200,39 +200,6 @@ extern layer_state_t layer_state;
# include "usbpd.h"
#endif
-// Function substitutions to ease GPIO manipulation
-#if defined(__AVR__)
-
-/* The AVR series GPIOs have a one clock read delay for changes in the digital input signal.
- * But here's more margin to make it two clocks. */
-# if !defined(GPIO_INPUT_PIN_DELAY)
-# define GPIO_INPUT_PIN_DELAY 2
-# endif
-# define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY)
-
-#elif defined(__ARMEL__) || defined(__ARMEB__)
-
-/* For GPIOs on ARM-based MCUs, the input pins are sampled by the clock of the bus
- * to which the GPIO is connected.
- * The connected buses differ depending on the various series of MCUs.
- * And since the instruction execution clock of the CPU and the bus clock of GPIO are different,
- * there is a delay of several clocks to read the change of the input signal.
- *
- * Define this delay with the GPIO_INPUT_PIN_DELAY macro.
- * If the GPIO_INPUT_PIN_DELAY macro is not defined, the following default values will be used.
- * (A fairly large value of 0.25 microseconds is set.)
- */
-# if !defined(GPIO_INPUT_PIN_DELAY)
-# if defined(STM32_SYSCLK)
-# define GPIO_INPUT_PIN_DELAY (STM32_SYSCLK / 1000000L / 4)
-# elif defined(KINETIS_SYSCLK_FREQUENCY)
-# define GPIO_INPUT_PIN_DELAY (KINETIS_SYSCLK_FREQUENCY / 1000000L / 4)
-# endif
-# endif
-# define waitInputPinDelay() wait_cpuclock(GPIO_INPUT_PIN_DELAY)
-
-#endif
-
// For tri-layer
void update_tri_layer(uint8_t layer1, uint8_t layer2, uint8_t layer3);
layer_state_t update_tri_layer_state(layer_state_t state, uint8_t layer1, uint8_t layer2, uint8_t layer3);