diff options
| author | Joel Challis <git@zvecr.com> | 2019-07-16 09:30:53 +0100 |
|---|---|---|
| committer | skullydazed <skullydazed@users.noreply.github.com> | 2019-07-16 01:30:53 -0700 |
| commit | 4e375aa1f536e979a587534df0b6951fa39e8a30 (patch) | |
| tree | b858c1cecf7af98092f9abc02aa5f9b4cdf9bd0a /drivers/arm/i2c_master.h | |
| parent | f859375284f5a27f5b4f8cbe654e305ca3face17 (diff) | |
Add ARM I2Cv1 support to i2c_master (#6262)
* Add ARM I2Cv1 support to i2c_master
* Add I2Cv1 docs
Diffstat (limited to 'drivers/arm/i2c_master.h')
| -rw-r--r-- | drivers/arm/i2c_master.h | 64 |
1 files changed, 41 insertions, 23 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h index 1bb74c800f..2f40d4985f 100644 --- a/drivers/arm/i2c_master.h +++ b/drivers/arm/i2c_master.h @@ -22,10 +22,16 @@ * Please ensure that HAL_USE_I2C is TRUE in the halconf.h file and that * STM32_I2C_USE_I2C1 is TRUE in the mcuconf.h file. */ +#pragma once #include "ch.h" #include <hal.h> + +#if defined(STM32F1XX) || defined(STM32F1xx) || defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32L0xx) || defined(STM32L1xx) + #define USE_I2CV1 +#endif + #ifdef I2C1_BANK #define I2C1_SCL_BANK I2C1_BANK #define I2C1_SDA_BANK I2C1_BANK @@ -46,30 +52,42 @@ #define I2C1_SDA 7 #endif -// The default PAL alternate modes are used to signal that the pins are used for I2C -#ifndef I2C1_SCL_PAL_MODE - #define I2C1_SCL_PAL_MODE 4 -#endif -#ifndef I2C1_SDA_PAL_MODE - #define I2C1_SDA_PAL_MODE 4 -#endif +#ifdef USE_I2CV1 + #ifndef I2C1_OPMODE + #define I2C1_OPMODE OPMODE_I2C + #endif + #ifndef I2C1_CLOCK_SPEED + #define I2C1_CLOCK_SPEED 100000 /* 400000 */ + #endif + #ifndef I2C1_DUTY_CYCLE + #define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */ + #endif +#else + // The default PAL alternate modes are used to signal that the pins are used for I2C + #ifndef I2C1_SCL_PAL_MODE + #define I2C1_SCL_PAL_MODE 4 + #endif + #ifndef I2C1_SDA_PAL_MODE + #define I2C1_SDA_PAL_MODE 4 + #endif -// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock -// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html -#ifndef I2C1_TIMINGR_PRESC - #define I2C1_TIMINGR_PRESC 15U -#endif -#ifndef I2C1_TIMINGR_SCLDEL - #define I2C1_TIMINGR_SCLDEL 4U -#endif -#ifndef I2C1_TIMINGR_SDADEL - #define I2C1_TIMINGR_SDADEL 2U -#endif -#ifndef I2C1_TIMINGR_SCLH - #define I2C1_TIMINGR_SCLH 15U -#endif -#ifndef I2C1_TIMINGR_SCLL - #define I2C1_TIMINGR_SCLL 21U + // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock + // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html + #ifndef I2C1_TIMINGR_PRESC + #define I2C1_TIMINGR_PRESC 15U + #endif + #ifndef I2C1_TIMINGR_SCLDEL + #define I2C1_TIMINGR_SCLDEL 4U + #endif + #ifndef I2C1_TIMINGR_SDADEL + #define I2C1_TIMINGR_SDADEL 2U + #endif + #ifndef I2C1_TIMINGR_SCLH + #define I2C1_TIMINGR_SCLH 15U + #endif + #ifndef I2C1_TIMINGR_SCLL + #define I2C1_TIMINGR_SCLL 21U + #endif #endif #ifndef I2C_DRIVER |