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-rw-r--r--platforms/chibios/boards/BLACKPILL_STM32_F401/configs/bootloader_defs.h5
-rw-r--r--platforms/chibios/boards/BLACKPILL_STM32_F411/configs/bootloader_defs.h5
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F042X6/configs/bootloader_defs.h5
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F072XB/configs/bootloader_defs.h5
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F303XC/configs/bootloader_defs.h5
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h2
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h1
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_L432XC/board/board.mk9
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h10
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h267
-rw-r--r--platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h1
-rw-r--r--platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h12
-rw-r--r--platforms/chibios/boards/QMK_PROTON_C/configs/bootloader_defs.h7
-rw-r--r--platforms/chibios/bootloader.c145
-rw-r--r--platforms/chibios/bootloaders/gd32v_dfu.c40
-rw-r--r--platforms/chibios/bootloaders/halfkay.c (renamed from platforms/chibios/boards/GENERIC_STM32_G431XB/configs/config.h)20
-rw-r--r--platforms/chibios/bootloaders/kiibohd.c32
-rw-r--r--platforms/chibios/bootloaders/none.c23
-rw-r--r--platforms/chibios/bootloaders/stm32_dfu.c94
-rw-r--r--platforms/chibios/bootloaders/stm32duino.c21
-rw-r--r--platforms/chibios/bootloaders/tinyuf2.c34
-rw-r--r--platforms/chibios/drivers/i2c_master.c59
-rw-r--r--platforms/chibios/drivers/i2c_master.h61
-rw-r--r--platforms/chibios/drivers/serial.c19
-rw-r--r--platforms/chibios/drivers/serial_usart.c32
-rw-r--r--platforms/chibios/eeprom_teensy.c59
-rw-r--r--platforms/chibios/gpio.h24
-rw-r--r--platforms/chibios/suspend.c9
30 files changed, 627 insertions, 383 deletions
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/bootloader_defs.h b/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/bootloader_defs.h
deleted file mode 100644
index 4da3d39a32..0000000000
--- a/platforms/chibios/boards/BLACKPILL_STM32_F401/configs/bootloader_defs.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here:
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
diff --git a/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/bootloader_defs.h b/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/bootloader_defs.h
deleted file mode 100644
index 4da3d39a32..0000000000
--- a/platforms/chibios/boards/BLACKPILL_STM32_F411/configs/bootloader_defs.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here:
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
diff --git a/platforms/chibios/boards/GENERIC_STM32_F042X6/configs/bootloader_defs.h b/platforms/chibios/boards/GENERIC_STM32_F042X6/configs/bootloader_defs.h
deleted file mode 100644
index 25113425a6..0000000000
--- a/platforms/chibios/boards/GENERIC_STM32_F042X6/configs/bootloader_defs.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here:
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFFC400
diff --git a/platforms/chibios/boards/GENERIC_STM32_F072XB/configs/bootloader_defs.h b/platforms/chibios/boards/GENERIC_STM32_F072XB/configs/bootloader_defs.h
deleted file mode 100644
index dccd0fa5d1..0000000000
--- a/platforms/chibios/boards/GENERIC_STM32_F072XB/configs/bootloader_defs.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here (page 175):
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFFC800
diff --git a/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/bootloader_defs.h b/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/bootloader_defs.h
deleted file mode 100644
index 87ac7b10dc..0000000000
--- a/platforms/chibios/boards/GENERIC_STM32_F303XC/configs/bootloader_defs.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here:
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFFD800
diff --git a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
index cc52a953ed..90a41326a1 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F405XG/configs/config.h
@@ -17,7 +17,7 @@
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
+
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
index cc52a953ed..90a41326a1 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F407XE/configs/config.h
@@ -17,7 +17,7 @@
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
+
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
index cc52a953ed..90a41326a1 100644
--- a/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_F446XE/configs/config.h
@@ -17,7 +17,7 @@
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
+
#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
index c27c61b19a..fc9055ccfb 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L412XB/configs/config.h
@@ -17,7 +17,6 @@
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
diff --git a/platforms/chibios/boards/GENERIC_STM32_L432XC/board/board.mk b/platforms/chibios/boards/GENERIC_STM32_L432XC/board/board.mk
new file mode 100644
index 0000000000..1250385eb8
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_L432XC/board/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC/board.c
+
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ST_NUCLEO32_L432KC
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
new file mode 100644
index 0000000000..b1838b30a8
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/config.h
@@ -0,0 +1,10 @@
+// Copyright 2021 Nick Brassel (@tzarc)
+// SPDX-License-Identifier: GPL-2.0-or-later
+#pragma once
+
+// Fixup equivalent usages within QMK as the base board definitions only go up to high
+#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
+
+#ifndef EARLY_INIT_PERFORM_BOOTLOADER_JUMP
+# define EARLY_INIT_PERFORM_BOOTLOADER_JUMP TRUE
+#endif
diff --git a/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
new file mode 100644
index 0000000000..707134d49e
--- /dev/null
+++ b/platforms/chibios/boards/GENERIC_STM32_L432XC/configs/mcuconf.h
@@ -0,0 +1,267 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ * STM32L4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+#define STM32L4xx_MCUCONF
+#define STM32L432_MCUCONF
+#define STM32L433_MCUCONF
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_VOS STM32_VOS_RANGE1
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_HSI16_ENABLED TRUE
+#define STM32_HSI48_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED FALSE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_MSIPLL_ENABLED FALSE
+#define STM32_MSIRANGE STM32_MSIRANGE_4M
+#define STM32_MSISRANGE STM32_MSISRANGE_4M
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSI16
+#define STM32_PLLM_VALUE 1
+#define STM32_PLLN_VALUE 10
+#define STM32_PLLPDIV_VALUE 0
+#define STM32_PLLP_VALUE 7
+#define STM32_PLLQ_VALUE 2
+#define STM32_PLLR_VALUE 2
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV1
+#define STM32_PPRE2 STM32_PPRE2_DIV1
+#define STM32_STOPWUCK STM32_STOPWUCK_MSI
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_MCOPRE STM32_MCOPRE_DIV1
+#define STM32_LSCOSEL STM32_LSCOSEL_NOCLOCK
+#define STM32_PLLSAI1N_VALUE 24
+#define STM32_PLLSAI1PDIV_VALUE 0
+#define STM32_PLLSAI1P_VALUE 7
+#define STM32_PLLSAI1Q_VALUE 2
+#define STM32_PLLSAI1R_VALUE 2
+
+/*
+ * Peripherals clock sources.
+ */
+#define STM32_USART1SEL STM32_USART1SEL_SYSCLK
+#define STM32_USART2SEL STM32_USART2SEL_SYSCLK
+#define STM32_LPUART1SEL STM32_LPUART1SEL_SYSCLK
+#define STM32_I2C1SEL STM32_I2C1SEL_SYSCLK
+#define STM32_I2C3SEL STM32_I2C3SEL_SYSCLK
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK1
+#define STM32_SAI1SEL STM32_SAI1SEL_OFF
+#define STM32_CLK48SEL STM32_CLK48SEL_HSI48
+#define STM32_ADCSEL STM32_ADCSEL_SYSCLK
+#define STM32_SWPMI1SEL STM32_SWPMI1SEL_PCLK1
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#define STM32_IRQ_EXTI1635_38_PRIORITY 6
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#define STM32_IRQ_EXTI20_PRIORITY 6
+#define STM32_IRQ_EXTI21_22_PRIORITY 15
+
+#define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
+#define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
+#define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY 7
+#define STM32_IRQ_TIM2_PRIORITY 7
+#define STM32_IRQ_TIM6_PRIORITY 7
+#define STM32_IRQ_TIM7_PRIORITY 7
+
+#define STM32_IRQ_USART1_PRIORITY 12
+#define STM32_IRQ_USART2_PRIORITY 12
+#define STM32_IRQ_LPUART1_PRIORITY 12
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_COMPACT_SAMPLES FALSE
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC123_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC_ADC123_PRESC ADC_CCR_PRESC_DIV2
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM15 FALSE
+#define STM32_GPT_USE_TIM16 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM15 FALSE
+#define STM32_ICU_USE_TIM16 FALSE
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM15 FALSE
+#define STM32_PWM_USE_TIM16 FALSE
+
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE 32
+#define STM32_RTC_PRESS_VALUE 1024
+#define STM32_RTC_CR_INIT 0
+#define STM32_RTC_TAMPCR_INIT 0
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_LPUART1 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_LPUART1_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
+
+/*
+ * TRNG driver system settings.
+ */
+#define STM32_TRNG_USE_RNG1 FALSE
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_USB1 TRUE
+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
+#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
+#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+/*
+ * WSPI driver system settings.
+ */
+#define STM32_WSPI_USE_QUADSPI1 FALSE
+#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 1
+
+#endif /* MCUCONF_H */
diff --git a/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h b/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
index c27c61b19a..fc9055ccfb 100644
--- a/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
+++ b/platforms/chibios/boards/GENERIC_STM32_L433XC/configs/config.h
@@ -17,7 +17,6 @@
/* Address for jumping to bootloader on STM32 chips. */
/* It is chip dependent, the correct number can be looked up by checking against ST's application note AN2606.
*/
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
#define PAL_STM32_OSPEED_HIGHEST PAL_STM32_OSPEED_HIGH
diff --git a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h b/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h
deleted file mode 100644
index c929d2ad03..0000000000
--- a/platforms/chibios/boards/GENERIC_WB32_F3G71XX/configs/bootloader_defs.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Address for jumping to bootloader on WB32 chips. */
-/* It is chip dependent, the correct number can be looked up here:
- * http://www.westberrytech.com/down/mcu/data/WB32F3G71xx_rm.pdf
- */
-#ifndef WB32_BOOTLOADER_ADDRESS
-# undef STM32_BOOTLOADER_ADDRESS
-# define WB32_BOOTLOADER_ADDRESS 0x1FFFE000
-# define STM32_BOOTLOADER_ADDRESS WB32_BOOTLOADER_ADDRESS
-#else
-# undef STM32_BOOTLOADER_ADDRESS
-# define STM32_BOOTLOADER_ADDRESS WB32_BOOTLOADER_ADDRESS
-#endif
diff --git a/platforms/chibios/boards/QMK_PROTON_C/configs/bootloader_defs.h b/platforms/chibios/boards/QMK_PROTON_C/configs/bootloader_defs.h
deleted file mode 100644
index 3b0e9d20a6..0000000000
--- a/platforms/chibios/boards/QMK_PROTON_C/configs/bootloader_defs.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here:
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- * This also requires a patch to chibios:
- * <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFFD800
diff --git a/platforms/chibios/bootloader.c b/platforms/chibios/bootloader.c
deleted file mode 100644
index 58212948b0..0000000000
--- a/platforms/chibios/bootloader.c
+++ /dev/null
@@ -1,145 +0,0 @@
-#include "bootloader.h"
-
-#include <ch.h>
-#include <hal.h>
-#include "wait.h"
-
-/* This code should be checked whether it runs correctly on platforms */
-#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
-#define BOOTLOADER_MAGIC 0xDEADBEEF
-#define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4)
-
-#ifndef STM32_BOOTLOADER_DUAL_BANK
-# define STM32_BOOTLOADER_DUAL_BANK FALSE
-#endif
-
-#ifdef BOOTLOADER_TINYUF2
-
-# define DBL_TAP_MAGIC 0xf01669ef // From tinyuf2's board_api.h
-
-// defined by linker script
-extern uint32_t _board_dfu_dbl_tap[];
-# define DBL_TAP_REG _board_dfu_dbl_tap[0]
-
-void bootloader_jump(void) {
- DBL_TAP_REG = DBL_TAP_MAGIC;
- NVIC_SystemReset();
-}
-
-void enter_bootloader_mode_if_requested(void) { /* not needed, no two-stage reset */
-}
-
-#elif STM32_BOOTLOADER_DUAL_BANK
-
-// Need pin definitions
-# include "config_common.h"
-
-# ifndef STM32_BOOTLOADER_DUAL_BANK_GPIO
-# error "No STM32_BOOTLOADER_DUAL_BANK_GPIO defined, don't know which pin to toggle"
-# endif
-
-# ifndef STM32_BOOTLOADER_DUAL_BANK_POLARITY
-# define STM32_BOOTLOADER_DUAL_BANK_POLARITY 0
-# endif
-
-# ifndef STM32_BOOTLOADER_DUAL_BANK_DELAY
-# define STM32_BOOTLOADER_DUAL_BANK_DELAY 100000
-# endif
-
-extern uint32_t __ram0_end__;
-
-__attribute__((weak)) void bootloader_jump(void) {
- // For STM32 MCUs with dual-bank flash, and we're incapable of jumping to the bootloader. The first valid flash
- // bank is executed unconditionally after a reset, so it doesn't enter DFU unless BOOT0 is high. Instead, we do
- // it with hardware...in this case, we pull a GPIO high/low depending on the configuration, connects 3.3V to
- // BOOT0's RC charging circuit, lets it charge the capacitor, and issue a system reset. See the QMK discord
- // #hardware channel pins for an example circuit.
- palSetPadMode(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_MODE_OUTPUT_PUSHPULL);
-# if STM32_BOOTLOADER_DUAL_BANK_POLARITY
- palSetPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO));
-# else
- palClearPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO));
-# endif
-
- // Wait for a while for the capacitor to charge
- wait_ms(100);
-
- // Issue a system reset to get the ROM bootloader to execute, with BOOT0 high
- NVIC_SystemReset();
-}
-
-void enter_bootloader_mode_if_requested(void) {} // not needed at all, but if anybody attempts to invoke it....
-
-#elif defined(STM32_BOOTLOADER_ADDRESS) // STM32_BOOTLOADER_DUAL_BANK
-
-extern uint32_t __ram0_end__;
-
-__attribute__((weak)) void bootloader_jump(void) {
- *MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
- NVIC_SystemReset();
-}
-
-void enter_bootloader_mode_if_requested(void) {
- unsigned long *check = MAGIC_ADDR;
- if (*check == BOOTLOADER_MAGIC) {
- *check = 0;
- __set_CONTROL(0);
- __set_MSP(*(__IO uint32_t *)STM32_BOOTLOADER_ADDRESS);
- __enable_irq();
-
- typedef void (*BootJump_t)(void);
- BootJump_t boot_jump = *(BootJump_t *)(STM32_BOOTLOADER_ADDRESS + 4);
- boot_jump();
- while (1)
- ;
- }
-}
-
-#elif defined(GD32VF103)
-
-# define DBGMCU_KEY_UNLOCK 0x4B5A6978
-# define DBGMCU_CMD_RESET 0x1
-
-__IO uint32_t *DBGMCU_KEY = (uint32_t *)DBGMCU_BASE + 0x0CU;
-__IO uint32_t *DBGMCU_CMD = (uint32_t *)DBGMCU_BASE + 0x08U;
-
-__attribute__((weak)) void bootloader_jump(void) {
- /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
- * register to generate a software reset request.
- * BUT instead two undocumented registers in the debug peripheral
- * that allow issueing a software reset. WHO would need the MSFRST
- * register anyway? Source:
- * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h */
- *DBGMCU_KEY = DBGMCU_KEY_UNLOCK;
- *DBGMCU_CMD = DBGMCU_CMD_RESET;
-}
-
-void enter_bootloader_mode_if_requested(void) { /* Jumping to bootloader is not possible from user code. */
-}
-
-#elif defined(KL2x) || defined(K20x) || defined(MK66F18) || defined(MIMXRT1062) // STM32_BOOTLOADER_DUAL_BANK // STM32_BOOTLOADER_ADDRESS
-/* Kinetis */
-
-# if defined(BOOTLOADER_KIIBOHD)
-/* Kiibohd Bootloader (MCHCK and Infinity KB) */
-# define SCB_AIRCR_VECTKEY_WRITEMAGIC 0x05FA0000
-const uint8_t sys_reset_to_loader_magic[] = "\xff\x00\x7fRESET TO LOADER\x7f\x00\xff\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
-__attribute__((weak)) void bootloader_jump(void) {
- void *volatile vbat = (void *)VBAT;
- __builtin_memcpy(vbat, (const void *)sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic));
- // request reset
- SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
-}
-
-# else /* defined(BOOTLOADER_KIIBOHD) */
-/* Default for Kinetis - expecting an ARM Teensy */
-# include "wait.h"
-__attribute__((weak)) void bootloader_jump(void) {
- wait_ms(100);
- __BKPT(0);
-}
-# endif /* defined(BOOTLOADER_KIIBOHD) */
-
-#else /* neither STM32 nor KINETIS */
-__attribute__((weak)) void bootloader_jump(void) {}
-#endif
diff --git a/platforms/chibios/bootloaders/gd32v_dfu.c b/platforms/chibios/bootloaders/gd32v_dfu.c
new file mode 100644
index 0000000000..baa7d1f882
--- /dev/null
+++ b/platforms/chibios/bootloaders/gd32v_dfu.c
@@ -0,0 +1,40 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#include <ch.h>
+#include <hal.h>
+
+#define DBGMCU_KEY_UNLOCK 0x4B5A6978
+#define DBGMCU_CMD_RESET 0x1
+
+__IO uint32_t *DBGMCU_KEY = (uint32_t *)DBGMCU_BASE + 0x0CU;
+__IO uint32_t *DBGMCU_CMD = (uint32_t *)DBGMCU_BASE + 0x08U;
+
+__attribute__((weak)) void bootloader_jump(void) {
+ /* The MTIMER unit of the GD32VF103 doesn't have the MSFRST
+ * register to generate a software reset request.
+ * BUT instead two undocumented registers in the debug peripheral
+ * that allow issueing a software reset. WHO would need the MSFRST
+ * register anyway? Source:
+ * https://github.com/esmil/gd32vf103inator/blob/master/include/gd32vf103/dbg.h */
+ *DBGMCU_KEY = DBGMCU_KEY_UNLOCK;
+ *DBGMCU_CMD = DBGMCU_CMD_RESET;
+}
+
+/* Jumping to bootloader is not possible from user code. */
+void enter_bootloader_mode_if_requested(void) {}
diff --git a/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/config.h b/platforms/chibios/bootloaders/halfkay.c
index 39ce627e77..168c2abc23 100644
--- a/platforms/chibios/boards/GENERIC_STM32_G431XB/configs/config.h
+++ b/platforms/chibios/bootloaders/halfkay.c
@@ -1,8 +1,8 @@
-/* Copyright 2018-2020 Nick Brassel (@tzarc)
+/* Copyright 2021 QMK
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 2 of the License, or
+ * the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
@@ -14,10 +14,12 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-/* Address for jumping to bootloader on STM32 chips. */
-/* It is chip dependent, the correct number can be looked up here (page 175):
- * http://www.st.com/web/en/resource/technical/document/application_note/CD00167594.pdf
- * This also requires a patch to chibios:
- * <tmk_dir>/tmk_core/tool/chibios/ch-bootloader-jump.patch
- */
-#define STM32_BOOTLOADER_ADDRESS 0x1FFF0000
+#include "bootloader.h"
+
+#include <ch.h>
+#include "wait.h"
+
+__attribute__((weak)) void bootloader_jump(void) {
+ wait_ms(100);
+ __BKPT(0);
+}
diff --git a/platforms/chibios/bootloaders/kiibohd.c b/platforms/chibios/bootloaders/kiibohd.c
new file mode 100644
index 0000000000..911e807092
--- /dev/null
+++ b/platforms/chibios/bootloaders/kiibohd.c
@@ -0,0 +1,32 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#include <ch.h>
+
+/* Kiibohd Bootloader (MCHCK and Infinity KB) */
+#define SCB_AIRCR_VECTKEY_WRITEMAGIC 0x05FA0000
+
+const uint8_t sys_reset_to_loader_magic[] = "\xff\x00\x7fRESET TO LOADER\x7f\x00\xff\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
+
+__attribute__((weak)) void bootloader_jump(void) {
+ void *volatile vbat = (void *)VBAT;
+ __builtin_memcpy(vbat, (const void *)sys_reset_to_loader_magic, sizeof(sys_reset_to_loader_magic));
+
+ // request reset
+ SCB->AIRCR = SCB_AIRCR_VECTKEY_WRITEMAGIC | SCB_AIRCR_SYSRESETREQ_Msk;
+}
diff --git a/platforms/chibios/bootloaders/none.c b/platforms/chibios/bootloaders/none.c
new file mode 100644
index 0000000000..8379d35abf
--- /dev/null
+++ b/platforms/chibios/bootloaders/none.c
@@ -0,0 +1,23 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#pragma message "Unknown bootloader set, you may not be able to enter bootloader using software reset"
+
+__attribute__((weak)) void bootloader_jump(void) {}
+
+__attribute__((weak)) void enter_bootloader_mode_if_requested(void) {}
diff --git a/platforms/chibios/bootloaders/stm32_dfu.c b/platforms/chibios/bootloaders/stm32_dfu.c
new file mode 100644
index 0000000000..0a113570f7
--- /dev/null
+++ b/platforms/chibios/bootloaders/stm32_dfu.c
@@ -0,0 +1,94 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#include <ch.h>
+#include <hal.h>
+#include "wait.h"
+
+extern uint32_t __ram0_end__;
+
+#ifndef STM32_BOOTLOADER_DUAL_BANK
+# define STM32_BOOTLOADER_DUAL_BANK FALSE
+#endif
+
+#if STM32_BOOTLOADER_DUAL_BANK
+# include "config_common.h"
+
+# ifndef STM32_BOOTLOADER_DUAL_BANK_GPIO
+# error "No STM32_BOOTLOADER_DUAL_BANK_GPIO defined, don't know which pin to toggle"
+# endif
+
+# ifndef STM32_BOOTLOADER_DUAL_BANK_POLARITY
+# define STM32_BOOTLOADER_DUAL_BANK_POLARITY 0
+# endif
+
+# ifndef STM32_BOOTLOADER_DUAL_BANK_DELAY
+# define STM32_BOOTLOADER_DUAL_BANK_DELAY 100000
+# endif
+
+__attribute__((weak)) void bootloader_jump(void) {
+ // For STM32 MCUs with dual-bank flash, and we're incapable of jumping to the bootloader. The first valid flash
+ // bank is executed unconditionally after a reset, so it doesn't enter DFU unless BOOT0 is high. Instead, we do
+ // it with hardware...in this case, we pull a GPIO high/low depending on the configuration, connects 3.3V to
+ // BOOT0's RC charging circuit, lets it charge the capacitor, and issue a system reset. See the QMK discord
+ // #hardware channel pins for an example circuit.
+ palSetPadMode(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_MODE_OUTPUT_PUSHPULL);
+# if STM32_BOOTLOADER_DUAL_BANK_POLARITY
+ palSetPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO));
+# else
+ palClearPad(PAL_PORT(STM32_BOOTLOADER_DUAL_BANK_GPIO), PAL_PAD(STM32_BOOTLOADER_DUAL_BANK_GPIO));
+# endif
+
+ // Wait for a while for the capacitor to charge
+ wait_ms(100);
+
+ // Issue a system reset to get the ROM bootloader to execute, with BOOT0 high
+ NVIC_SystemReset();
+}
+
+// not needed at all, but if anybody attempts to invoke it....
+void enter_bootloader_mode_if_requested(void) {}
+
+#else
+
+/* This code should be checked whether it runs correctly on platforms */
+# define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
+# define BOOTLOADER_MAGIC 0xDEADBEEF
+# define MAGIC_ADDR (unsigned long *)(SYMVAL(__ram0_end__) - 4)
+
+__attribute__((weak)) void bootloader_jump(void) {
+ *MAGIC_ADDR = BOOTLOADER_MAGIC; // set magic flag => reset handler will jump into boot loader
+ NVIC_SystemReset();
+}
+
+void enter_bootloader_mode_if_requested(void) {
+ unsigned long *check = MAGIC_ADDR;
+ if (*check == BOOTLOADER_MAGIC) {
+ *check = 0;
+ __set_CONTROL(0);
+ __set_MSP(*(__IO uint32_t *)STM32_BOOTLOADER_ADDRESS);
+ __enable_irq();
+
+ typedef void (*BootJump_t)(void);
+ BootJump_t boot_jump = *(BootJump_t *)(STM32_BOOTLOADER_ADDRESS + 4);
+ boot_jump();
+ while (1)
+ ;
+ }
+}
+#endif
diff --git a/platforms/chibios/bootloaders/stm32duino.c b/platforms/chibios/bootloaders/stm32duino.c
new file mode 100644
index 0000000000..dd1d551fa9
--- /dev/null
+++ b/platforms/chibios/bootloaders/stm32duino.c
@@ -0,0 +1,21 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#include <ch.h>
+
+__attribute__((weak)) void bootloader_jump(void) { NVIC_SystemReset(); }
diff --git a/platforms/chibios/bootloaders/tinyuf2.c b/platforms/chibios/bootloaders/tinyuf2.c
new file mode 100644
index 0000000000..9ffca5dec8
--- /dev/null
+++ b/platforms/chibios/bootloaders/tinyuf2.c
@@ -0,0 +1,34 @@
+/* Copyright 2021 QMK
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bootloader.h"
+
+#include <ch.h>
+
+// From tinyuf2's board_api.h
+#define DBL_TAP_MAGIC 0xF01669EF
+
+// defined by linker script
+extern uint32_t _board_dfu_dbl_tap[];
+#define DBL_TAP_REG _board_dfu_dbl_tap[0]
+
+__attribute__((weak)) void bootloader_jump(void) {
+ DBL_TAP_REG = DBL_TAP_MAGIC;
+ NVIC_SystemReset();
+}
+
+/* not needed, no two-stage reset */
+void enter_bootloader_mode_if_requested(void) {}
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
index 43591d56f8..4a5d4760d0 100644
--- a/platforms/chibios/drivers/i2c_master.c
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -27,8 +27,67 @@
#include "quantum.h"
#include "i2c_master.h"
#include <string.h>
+#include <ch.h>
#include <hal.h>
+#ifndef I2C1_SCL_PIN
+# define I2C1_SCL_PIN B6
+#endif
+#ifndef I2C1_SDA_PIN
+# define I2C1_SDA_PIN B7
+#endif
+
+#ifdef USE_I2CV1
+# ifndef I2C1_OPMODE
+# define I2C1_OPMODE OPMODE_I2C
+# endif
+# ifndef I2C1_CLOCK_SPEED
+# define I2C1_CLOCK_SPEED 100000 /* 400000 */
+# endif
+# ifndef I2C1_DUTY_CYCLE
+# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
+# endif
+#else
+// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
+// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+# ifndef I2C1_TIMINGR_PRESC
+# define I2C1_TIMINGR_PRESC 0U
+# endif
+# ifndef I2C1_TIMINGR_SCLDEL
+# define I2C1_TIMINGR_SCLDEL 7U
+# endif
+# ifndef I2C1_TIMINGR_SDADEL
+# define I2C1_TIMINGR_SDADEL 0U
+# endif
+# ifndef I2C1_TIMINGR_SCLH
+# define I2C1_TIMINGR_SCLH 38U
+# endif
+# ifndef I2C1_TIMINGR_SCLL
+# define I2C1_TIMINGR_SCLL 129U
+# endif
+#endif
+
+#ifndef I2C_DRIVER
+# define I2C_DRIVER I2CD1
+#endif
+
+#ifdef USE_GPIOV1
+# ifndef I2C1_SCL_PAL_MODE
+# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
+# endif
+# ifndef I2C1_SDA_PAL_MODE
+# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
+# endif
+#else
+// The default PAL alternate modes are used to signal that the pins are used for I2C
+# ifndef I2C1_SCL_PAL_MODE
+# define I2C1_SCL_PAL_MODE 4
+# endif
+# ifndef I2C1_SDA_PAL_MODE
+# define I2C1_SDA_PAL_MODE 4
+# endif
+#endif
+
static uint8_t i2c_address;
static const I2CConfig i2cconfig = {
diff --git a/platforms/chibios/drivers/i2c_master.h b/platforms/chibios/drivers/i2c_master.h
index 5f082e9d1e..deee7ecc08 100644
--- a/platforms/chibios/drivers/i2c_master.h
+++ b/platforms/chibios/drivers/i2c_master.h
@@ -24,66 +24,7 @@
*/
#pragma once
-#include <ch.h>
-#include <hal.h>
-
-#ifndef I2C1_SCL_PIN
-# define I2C1_SCL_PIN B6
-#endif
-#ifndef I2C1_SDA_PIN
-# define I2C1_SDA_PIN B7
-#endif
-
-#ifdef USE_I2CV1
-# ifndef I2C1_OPMODE
-# define I2C1_OPMODE OPMODE_I2C
-# endif
-# ifndef I2C1_CLOCK_SPEED
-# define I2C1_CLOCK_SPEED 100000 /* 400000 */
-# endif
-# ifndef I2C1_DUTY_CYCLE
-# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
-# endif
-#else
-// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
-// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
-# ifndef I2C1_TIMINGR_PRESC
-# define I2C1_TIMINGR_PRESC 0U
-# endif
-# ifndef I2C1_TIMINGR_SCLDEL
-# define I2C1_TIMINGR_SCLDEL 7U
-# endif
-# ifndef I2C1_TIMINGR_SDADEL
-# define I2C1_TIMINGR_SDADEL 0U
-# endif
-# ifndef I2C1_TIMINGR_SCLH
-# define I2C1_TIMINGR_SCLH 38U
-# endif
-# ifndef I2C1_TIMINGR_SCLL
-# define I2C1_TIMINGR_SCLL 129U
-# endif
-#endif
-
-#ifndef I2C_DRIVER
-# define I2C_DRIVER I2CD1
-#endif
-
-#ifdef USE_GPIOV1
-# ifndef I2C1_SCL_PAL_MODE
-# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
-# endif
-# ifndef I2C1_SDA_PAL_MODE
-# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
-# endif
-#else
-// The default PAL alternate modes are used to signal that the pins are used for I2C
-# ifndef I2C1_SCL_PAL_MODE
-# define I2C1_SCL_PAL_MODE 4
-# endif
-# ifndef I2C1_SDA_PAL_MODE
-# define I2C1_SDA_PAL_MODE 4
-# endif
-#endif
+#include <stdint.h>
typedef int16_t i2c_status_t;
diff --git a/platforms/chibios/drivers/serial.c b/platforms/chibios/drivers/serial.c
index ef6f0aa8d5..17d0b32be8 100644
--- a/platforms/chibios/drivers/serial.c
+++ b/platforms/chibios/drivers/serial.c
@@ -179,8 +179,6 @@ void interrupt_handler(void *arg) {
// wait for the sync to finish sending
serial_delay();
- *trans->status = (checksum_computed == checksum_received) ? TRANSACTION_ACCEPTED : TRANSACTION_DATA_ERROR;
-
// end transaction
serial_input();
@@ -193,17 +191,12 @@ void interrupt_handler(void *arg) {
/////////
// start transaction by initiator
//
-// int soft_serial_transaction(int sstd_index)
+// bool soft_serial_transaction(int sstd_index)
//
-// Returns:
-// TRANSACTION_END
-// TRANSACTION_NO_RESPONSE
-// TRANSACTION_DATA_ERROR
// this code is very time dependent, so we need to disable interrupts
-int soft_serial_transaction(int sstd_index) {
- if (sstd_index > NUM_TOTAL_TRANSACTIONS) return TRANSACTION_TYPE_ERROR;
+bool soft_serial_transaction(int sstd_index) {
+ if (sstd_index > NUM_TOTAL_TRANSACTIONS) return false;
split_transaction_desc_t *trans = &split_transaction_table[sstd_index];
- if (!trans->status) return TRANSACTION_TYPE_ERROR; // not registered
// TODO: remove extra delay between transactions
serial_delay();
@@ -226,7 +219,7 @@ int soft_serial_transaction(int sstd_index) {
// slave failed to pull the line low, assume not present
dprintf("serial::NO_RESPONSE\n");
chSysUnlock();
- return TRANSACTION_NO_RESPONSE;
+ return false;
}
// if the slave is present syncronize with it
@@ -266,7 +259,7 @@ int soft_serial_transaction(int sstd_index) {
serial_high();
chSysUnlock();
- return TRANSACTION_DATA_ERROR;
+ return false;
}
// always, release the line when not in use
@@ -274,5 +267,5 @@ int soft_serial_transaction(int sstd_index) {
serial_output();
chSysUnlock();
- return TRANSACTION_END;
+ return true;
}
diff --git a/platforms/chibios/drivers/serial_usart.c b/platforms/chibios/drivers/serial_usart.c
index 124e4be685..42c476a374 100644
--- a/platforms/chibios/drivers/serial_usart.c
+++ b/platforms/chibios/drivers/serial_usart.c
@@ -36,7 +36,7 @@ static SerialDriver* serial_driver = &SERIAL_USART_DRIVER;
static inline bool react_to_transactions(void);
static inline bool __attribute__((nonnull)) receive(uint8_t* destination, const size_t size);
static inline bool __attribute__((nonnull)) send(const uint8_t* source, const size_t size);
-static inline int initiate_transaction(uint8_t sstd_index);
+static inline bool initiate_transaction(uint8_t sstd_index);
static inline void usart_clear(void);
/**
@@ -206,14 +206,12 @@ static inline bool react_to_transactions(void) {
to signal that the slave is ready to receive possible transaction buffers */
sstd_index ^= HANDSHAKE_MAGIC;
if (!send(&sstd_index, sizeof(sstd_index))) {
- *trans->status = TRANSACTION_DATA_ERROR;
return false;
}
/* Receive transaction buffer from the master. If this transaction requires it.*/
if (trans->initiator2target_buffer_size) {
if (!receive(split_trans_initiator2target_buffer(trans), trans->initiator2target_buffer_size)) {
- *trans->status = TRANSACTION_DATA_ERROR;
return false;
}
}
@@ -226,12 +224,10 @@ static inline bool react_to_transactions(void) {
/* Send transaction buffer to the master. If this transaction requires it. */
if (trans->target2initiator_buffer_size) {
if (!send(split_trans_target2initiator_buffer(trans), trans->target2initiator_buffer_size)) {
- *trans->status = TRANSACTION_DATA_ERROR;
return false;
}
}
- *trans->status = TRANSACTION_ACCEPTED;
return true;
}
@@ -252,11 +248,9 @@ void soft_serial_initiator_init(void) {
* @brief Start transaction from the master half to the slave half.
*
* @param index Transaction Table index of the transaction to start.
- * @return int TRANSACTION_NO_RESPONSE in case of Timeout.
- * TRANSACTION_TYPE_ERROR in case of invalid transaction index.
- * TRANSACTION_END in case of success.
+ * @return bool Indicates success of transaction.
*/
-int soft_serial_transaction(int index) {
+bool soft_serial_transaction(int index) {
/* Clear the receive queue, to start with a clean slate.
* Parts of failed transactions or spurious bytes could still be in it. */
usart_clear();
@@ -266,25 +260,19 @@ int soft_serial_transaction(int index) {
/**
* @brief Initiate transaction to slave half.
*/
-static inline int initiate_transaction(uint8_t sstd_index) {
+static inline bool initiate_transaction(uint8_t sstd_index) {
/* Sanity check that we are actually starting a valid transaction. */
if (sstd_index >= NUM_TOTAL_TRANSACTIONS) {
dprintln("USART: Illegal transaction Id.");
- return TRANSACTION_TYPE_ERROR;
+ return false;
}
split_transaction_desc_t* trans = &split_transaction_table[sstd_index];
- /* Transaction is not registered. Abort. */
- if (!trans->status) {
- dprintln("USART: Transaction not registered.");
- return TRANSACTION_TYPE_ERROR;
- }
-
/* Send transaction table index to the slave, which doubles as basic handshake token. */
if (!send(&sstd_index, sizeof(sstd_index))) {
dprintln("USART: Send Handshake failed.");
- return TRANSACTION_TYPE_ERROR;
+ return false;
}
uint8_t sstd_index_shake = 0xFF;
@@ -295,14 +283,14 @@ static inline int initiate_transaction(uint8_t sstd_index) {
*/
if (!receive(&sstd_index_shake, sizeof(sstd_index_shake)) || (sstd_index_shake != (sstd_index ^ HANDSHAKE_MAGIC))) {
dprintln("USART: Handshake failed.");
- return TRANSACTION_NO_RESPONSE;
+ return false;
}
/* Send transaction buffer to the slave. If this transaction requires it. */
if (trans->initiator2target_buffer_size) {
if (!send(split_trans_initiator2target_buffer(trans), trans->initiator2target_buffer_size)) {
dprintln("USART: Send failed.");
- return TRANSACTION_NO_RESPONSE;
+ return false;
}
}
@@ -310,9 +298,9 @@ static inline int initiate_transaction(uint8_t sstd_index) {
if (trans->target2initiator_buffer_size) {
if (!receive(split_trans_target2initiator_buffer(trans), trans->target2initiator_buffer_size)) {
dprintln("USART: Receive failed.");
- return TRANSACTION_NO_RESPONSE;
+ return false;
}
}
- return TRANSACTION_END;
+ return true;
}
diff --git a/platforms/chibios/eeprom_teensy.c b/platforms/chibios/eeprom_teensy.c
index 4aaf665269..2093f9b4b2 100644
--- a/platforms/chibios/eeprom_teensy.c
+++ b/platforms/chibios/eeprom_teensy.c
@@ -524,64 +524,7 @@ void eeprom_write_block(const void *buf, void *addr, uint32_t len) {
}
#else
-// No EEPROM supported, so emulate it
-
-# ifndef EEPROM_SIZE
-# include "eeconfig.h"
-# define EEPROM_SIZE (((EECONFIG_SIZE + 3) / 4) * 4) // based off eeconfig's current usage, aligned to 4-byte sizes, to deal with LTO
-# endif
-__attribute__((aligned(4))) static uint8_t buffer[EEPROM_SIZE];
-
-uint8_t eeprom_read_byte(const uint8_t *addr) {
- uint32_t offset = (uint32_t)addr;
- return buffer[offset];
-}
-
-void eeprom_write_byte(uint8_t *addr, uint8_t value) {
- uint32_t offset = (uint32_t)addr;
- buffer[offset] = value;
-}
-
-uint16_t eeprom_read_word(const uint16_t *addr) {
- const uint8_t *p = (const uint8_t *)addr;
- return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8);
-}
-
-uint32_t eeprom_read_dword(const uint32_t *addr) {
- const uint8_t *p = (const uint8_t *)addr;
- return eeprom_read_byte(p) | (eeprom_read_byte(p + 1) << 8) | (eeprom_read_byte(p + 2) << 16) | (eeprom_read_byte(p + 3) << 24);
-}
-
-void eeprom_read_block(void *buf, const void *addr, size_t len) {
- const uint8_t *p = (const uint8_t *)addr;
- uint8_t * dest = (uint8_t *)buf;
- while (len--) {
- *dest++ = eeprom_read_byte(p++);
- }
-}
-
-void eeprom_write_word(uint16_t *addr, uint16_t value) {
- uint8_t *p = (uint8_t *)addr;
- eeprom_write_byte(p++, value);
- eeprom_write_byte(p, value >> 8);
-}
-
-void eeprom_write_dword(uint32_t *addr, uint32_t value) {
- uint8_t *p = (uint8_t *)addr;
- eeprom_write_byte(p++, value);
- eeprom_write_byte(p++, value >> 8);
- eeprom_write_byte(p++, value >> 16);
- eeprom_write_byte(p, value >> 24);
-}
-
-void eeprom_write_block(const void *buf, void *addr, size_t len) {
- uint8_t * p = (uint8_t *)addr;
- const uint8_t *src = (const uint8_t *)buf;
- while (len--) {
- eeprom_write_byte(p++, *src++);
- }
-}
-
+# error Unsupported Teensy EEPROM.
#endif /* chip selection */
// The update functions just calls write for now, but could probably be optimized
diff --git a/platforms/chibios/gpio.h b/platforms/chibios/gpio.h
index 4d057f1cab..eb44a18f9c 100644
--- a/platforms/chibios/gpio.h
+++ b/platforms/chibios/gpio.h
@@ -22,10 +22,12 @@ typedef ioline_t pin_t;
/* Operation of GPIO by pin. */
-#define setPinInput(pin) palSetLineMode(pin, PAL_MODE_INPUT)
-#define setPinInputHigh(pin) palSetLineMode(pin, PAL_MODE_INPUT_PULLUP)
-#define setPinInputLow(pin) palSetLineMode(pin, PAL_MODE_INPUT_PULLDOWN)
-#define setPinOutput(pin) palSetLineMode(pin, PAL_MODE_OUTPUT_PUSHPULL)
+#define setPinInput(pin) palSetLineMode((pin), PAL_MODE_INPUT)
+#define setPinInputHigh(pin) palSetLineMode((pin), PAL_MODE_INPUT_PULLUP)
+#define setPinInputLow(pin) palSetLineMode((pin), PAL_MODE_INPUT_PULLDOWN)
+#define setPinOutputPushPull(pin) palSetLineMode((pin), PAL_MODE_OUTPUT_PUSHPULL)
+#define setPinOutputOpenDrain(pin) palSetLineMode((pin), PAL_MODE_OUTPUT_OPENDRAIN)
+#define setPinOutput(pin) setPinOutputPushPull(pin)
#define writePinHigh(pin) palSetLine(pin)
#define writePinLow(pin) palClearLine(pin)
@@ -34,17 +36,3 @@ typedef ioline_t pin_t;
#define readPin(pin) palReadLine(pin)
#define togglePin(pin) palToggleLine(pin)
-
-/* Operation of GPIO by port. */
-
-typedef uint16_t port_data_t;
-
-#define readPort(pin) palReadPort(PAL_PORT(pin))
-
-#define setPortBitInput(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_INPUT)
-#define setPortBitInputHigh(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_INPUT_PULLUP)
-#define setPortBitInputLow(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_INPUT_PULLDOWN)
-#define setPortBitOutput(pin, bit) palSetPadMode(PAL_PORT(pin), bit, PAL_MODE_OUTPUT_PUSHPULL)
-
-#define writePortBitLow(pin, bit) palClearLine(PAL_LINE(PAL_PORT(pin), bit))
-#define writePortBitHigh(pin, bit) palSetLine(PAL_LINE(PAL_PORT(pin), bit))
diff --git a/platforms/chibios/suspend.c b/platforms/chibios/suspend.c
index 9310a99920..d10ddf4501 100644
--- a/platforms/chibios/suspend.c
+++ b/platforms/chibios/suspend.c
@@ -13,15 +13,6 @@
#include "led.h"
#include "wait.h"
-/** \brief suspend idle
- *
- * FIXME: needs doc
- */
-void suspend_idle(uint8_t time) {
- // TODO: this is not used anywhere - what units is 'time' in?
- wait_ms(time);
-}
-
/** \brief suspend power down
*
* FIXME: needs doc