diff options
| -rw-r--r-- | changelog.md | 1 | ||||
| -rw-r--r-- | drivers/arm/i2c_master.c | 16 | ||||
| -rw-r--r-- | drivers/arm/i2c_master.h | 40 |
3 files changed, 46 insertions, 11 deletions
diff --git a/changelog.md b/changelog.md index 1adbb7e9f0..187443e1cf 100644 --- a/changelog.md +++ b/changelog.md @@ -28,6 +28,7 @@ 05-29-2019 - Fixing matrix_scan so it properly returns changed status 05-29-2019 - Add belgian layour for sendstring (qmk#6008) 06-03-2019 - Overhaul of AutoShift feature (qmk#6067) +06-05-2019 - Parameterize STM32 I2C pin modes and timing parameters. (qmk#5671) 06-05-2019 - Fix compiler error for ATSAM based keyboards 06-05-2019 - Move RGB typedef's into a unified location 06-05-2019 - upgrade gcc-arm-none-eabi from the default 5.4.1 to 6.3.1 due to ARM runtine issues
\ No newline at end of file diff --git a/drivers/arm/i2c_master.c b/drivers/arm/i2c_master.c index 7369398cc4..5814375f37 100644 --- a/drivers/arm/i2c_master.c +++ b/drivers/arm/i2c_master.c @@ -32,12 +32,10 @@ static uint8_t i2c_address; -// This configures the I2C clock to 400khz assuming a 72Mhz clock -// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html static const I2CConfig i2cconfig = { - STM32_TIMINGR_PRESC(15U) | - STM32_TIMINGR_SCLDEL(4U) | STM32_TIMINGR_SDADEL(2U) | - STM32_TIMINGR_SCLH(15U) | STM32_TIMINGR_SCLL(21U), + STM32_TIMINGR_PRESC(I2C1_TIMINGR_PRESC) | + STM32_TIMINGR_SCLDEL(I2C1_TIMINGR_SCLDEL) | STM32_TIMINGR_SDADEL(I2C1_TIMINGR_SDADEL) | + STM32_TIMINGR_SCLH(I2C1_TIMINGR_SCLH) | STM32_TIMINGR_SCLL(I2C1_TIMINGR_SCLL), 0, 0 }; @@ -58,13 +56,13 @@ __attribute__ ((weak)) void i2c_init(void) { // Try releasing special pins for a short time - palSetPadMode(I2C1_BANK, I2C1_SCL, PAL_MODE_INPUT); - palSetPadMode(I2C1_BANK, I2C1_SDA, PAL_MODE_INPUT); + palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_INPUT); + palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_INPUT); chThdSleepMilliseconds(10); - palSetPadMode(I2C1_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); - palSetPadMode(I2C1_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(4) | PAL_STM32_OTYPE_OPENDRAIN); + palSetPadMode(I2C1_SCL_BANK, I2C1_SCL, PAL_MODE_ALTERNATE(I2C1_SCL_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN); + palSetPadMode(I2C1_SDA_BANK, I2C1_SDA, PAL_MODE_ALTERNATE(I2C1_SDA_PAL_MODE) | PAL_STM32_OTYPE_OPENDRAIN); //i2cInit(); //This is invoked by halInit() so no need to redo it. } diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h index a15f1702dd..1bb74c800f 100644 --- a/drivers/arm/i2c_master.h +++ b/drivers/arm/i2c_master.h @@ -26,9 +26,19 @@ #include "ch.h" #include <hal.h> -#ifndef I2C1_BANK - #define I2C1_BANK GPIOB +#ifdef I2C1_BANK + #define I2C1_SCL_BANK I2C1_BANK + #define I2C1_SDA_BANK I2C1_BANK #endif + +#ifndef I2C1_SCL_BANK + #define I2C1_SCL_BANK GPIOB +#endif + +#ifndef I2C1_SDA_BANK + #define I2C1_SDA_BANK GPIOB +#endif + #ifndef I2C1_SCL #define I2C1_SCL 6 #endif @@ -36,6 +46,32 @@ #define I2C1_SDA 7 #endif +// The default PAL alternate modes are used to signal that the pins are used for I2C +#ifndef I2C1_SCL_PAL_MODE + #define I2C1_SCL_PAL_MODE 4 +#endif +#ifndef I2C1_SDA_PAL_MODE + #define I2C1_SDA_PAL_MODE 4 +#endif + +// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock +// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html +#ifndef I2C1_TIMINGR_PRESC + #define I2C1_TIMINGR_PRESC 15U +#endif +#ifndef I2C1_TIMINGR_SCLDEL + #define I2C1_TIMINGR_SCLDEL 4U +#endif +#ifndef I2C1_TIMINGR_SDADEL + #define I2C1_TIMINGR_SDADEL 2U +#endif +#ifndef I2C1_TIMINGR_SCLH + #define I2C1_TIMINGR_SCLH 15U +#endif +#ifndef I2C1_TIMINGR_SCLL + #define I2C1_TIMINGR_SCLL 21U +#endif + #ifndef I2C_DRIVER #define I2C_DRIVER I2CD1 #endif |