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authorskullY <skullydazed@gmail.com>2019-08-30 11:19:03 -0700
committerFlorian Didron <fdidron@users.noreply.github.com>2019-10-01 10:21:12 +0900
commit93f6749e06b70ba81e15f8b77e5a18675dacddfe (patch)
treefcf75ef930800a948e5a3ba015d6759889f2284d /quantum/stm32
parentda34bddba16ba7a8495dc30bfe4542551ba87ed4 (diff)
clang-format changes
Diffstat (limited to 'quantum/stm32')
-rw-r--r--quantum/stm32/chconf.h132
-rw-r--r--quantum/stm32/halconf.h244
-rw-r--r--quantum/stm32/mcuconf.h312
3 files changed, 338 insertions, 350 deletions
diff --git a/quantum/stm32/chconf.h b/quantum/stm32/chconf.h
index edb697d4da..8fcb55d408 100644
--- a/quantum/stm32/chconf.h
+++ b/quantum/stm32/chconf.h
@@ -26,9 +26,9 @@
*/
#ifndef CHCONF_H
-#define CHCONF_H
+# define CHCONF_H
-#define _CHIBIOS_RT_CONF_
+# define _CHIBIOS_RT_CONF_
/*===========================================================================*/
/**
@@ -41,14 +41,14 @@
* @brief System time counter resolution.
* @note Allowed values are 16 or 32 bits.
*/
-#define CH_CFG_ST_RESOLUTION 32
+# define CH_CFG_ST_RESOLUTION 32
/**
* @brief System tick frequency.
* @details Frequency of the system timer that drives the system ticks. This
* setting also defines the system tick time unit.
*/
-#define CH_CFG_ST_FREQUENCY 100000
+# define CH_CFG_ST_FREQUENCY 100000
/**
* @brief Time delta constant for the tick-less mode.
@@ -58,7 +58,7 @@
* The value one is not valid, timeouts are rounded up to
* this value.
*/
-#define CH_CFG_ST_TIMEDELTA 0
+# define CH_CFG_ST_TIMEDELTA 0
/** @} */
@@ -81,7 +81,7 @@
* @note The round robin preemption is not supported in tickless mode and
* must be set to zero in that case.
*/
-#define CH_CFG_TIME_QUANTUM 0
+# define CH_CFG_TIME_QUANTUM 0
/**
* @brief Managed RAM size.
@@ -94,7 +94,7 @@
* provide the @p __heap_base__ and @p __heap_end__ symbols.
* @note Requires @p CH_CFG_USE_MEMCORE.
*/
-#define CH_CFG_MEMCORE_SIZE 0
+# define CH_CFG_MEMCORE_SIZE 0
/**
* @brief Idle thread automatic spawn suppression.
@@ -103,7 +103,7 @@
* function becomes the idle thread and must implement an
* infinite loop.
*/
-#define CH_CFG_NO_IDLE_THREAD FALSE
+# define CH_CFG_NO_IDLE_THREAD FALSE
/** @} */
@@ -122,7 +122,7 @@
* @note This is not related to the compiler optimization options.
* @note The default is @p TRUE.
*/
-#define CH_CFG_OPTIMIZE_SPEED TRUE
+# define CH_CFG_OPTIMIZE_SPEED TRUE
/** @} */
@@ -140,7 +140,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_TM TRUE
+# define CH_CFG_USE_TM TRUE
/**
* @brief Threads registry APIs.
@@ -148,7 +148,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_REGISTRY TRUE
+# define CH_CFG_USE_REGISTRY TRUE
/**
* @brief Threads synchronization APIs.
@@ -157,7 +157,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_WAITEXIT TRUE
+# define CH_CFG_USE_WAITEXIT TRUE
/**
* @brief Semaphores APIs.
@@ -165,7 +165,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_SEMAPHORES TRUE
+# define CH_CFG_USE_SEMAPHORES TRUE
/**
* @brief Semaphores queuing mode.
@@ -176,7 +176,7 @@
* requirements.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
+# define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE
/**
* @brief Mutexes APIs.
@@ -184,7 +184,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_MUTEXES TRUE
+# define CH_CFG_USE_MUTEXES TRUE
/**
* @brief Enables recursive behavior on mutexes.
@@ -194,7 +194,7 @@
* @note The default is @p FALSE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
+# define CH_CFG_USE_MUTEXES_RECURSIVE FALSE
/**
* @brief Conditional Variables APIs.
@@ -204,7 +204,7 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_MUTEXES.
*/
-#define CH_CFG_USE_CONDVARS TRUE
+# define CH_CFG_USE_CONDVARS TRUE
/**
* @brief Conditional Variables APIs with timeout.
@@ -214,7 +214,7 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_CONDVARS.
*/
-#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
+# define CH_CFG_USE_CONDVARS_TIMEOUT TRUE
/**
* @brief Events Flags APIs.
@@ -222,7 +222,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_EVENTS TRUE
+# define CH_CFG_USE_EVENTS TRUE
/**
* @brief Events Flags APIs with timeout.
@@ -232,7 +232,7 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_EVENTS.
*/
-#define CH_CFG_USE_EVENTS_TIMEOUT TRUE
+# define CH_CFG_USE_EVENTS_TIMEOUT TRUE
/**
* @brief Synchronous Messages APIs.
@@ -241,7 +241,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_MESSAGES TRUE
+# define CH_CFG_USE_MESSAGES TRUE
/**
* @brief Synchronous Messages queuing mode.
@@ -252,7 +252,7 @@
* requirements.
* @note Requires @p CH_CFG_USE_MESSAGES.
*/
-#define CH_CFG_USE_MESSAGES_PRIORITY TRUE
+# define CH_CFG_USE_MESSAGES_PRIORITY TRUE
/**
* @brief Mailboxes APIs.
@@ -262,7 +262,7 @@
* @note The default is @p TRUE.
* @note Requires @p CH_CFG_USE_SEMAPHORES.
*/
-#define CH_CFG_USE_MAILBOXES TRUE
+# define CH_CFG_USE_MAILBOXES TRUE
/**
* @brief Core Memory Manager APIs.
@@ -271,7 +271,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_MEMCORE TRUE
+# define CH_CFG_USE_MEMCORE TRUE
/**
* @brief Heap Allocator APIs.
@@ -283,7 +283,7 @@
* @p CH_CFG_USE_SEMAPHORES.
* @note Mutexes are recommended.
*/
-#define CH_CFG_USE_HEAP TRUE
+# define CH_CFG_USE_HEAP TRUE
/**
* @brief Memory Pools Allocator APIs.
@@ -292,7 +292,7 @@
*
* @note The default is @p TRUE.
*/
-#define CH_CFG_USE_MEMPOOLS TRUE
+# define CH_CFG_USE_MEMPOOLS TRUE
/**
* @brief Dynamic Threads APIs.
@@ -303,7 +303,7 @@
* @note Requires @p CH_CFG_USE_WAITEXIT.
* @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS.
*/
-#define CH_CFG_USE_DYNAMIC TRUE
+# define CH_CFG_USE_DYNAMIC TRUE
/** @} */
@@ -319,7 +319,7 @@
*
* @note The default is @p FALSE.
*/
-#define CH_DBG_STATISTICS FALSE
+# define CH_DBG_STATISTICS FALSE
/**
* @brief Debug option, system state check.
@@ -328,7 +328,7 @@
*
* @note The default is @p FALSE.
*/
-#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+# define CH_DBG_SYSTEM_STATE_CHECK FALSE
/**
* @brief Debug option, parameters checks.
@@ -337,7 +337,7 @@
*
* @note The default is @p FALSE.
*/
-#define CH_DBG_ENABLE_CHECKS FALSE
+# define CH_DBG_ENABLE_CHECKS FALSE
/**
* @brief Debug option, consistency checks.
@@ -347,7 +347,7 @@
*
* @note The default is @p FALSE.
*/
-#define CH_DBG_ENABLE_ASSERTS FALSE
+# define CH_DBG_ENABLE_ASSERTS FALSE
/**
* @brief Debug option, trace buffer.
@@ -355,14 +355,14 @@
*
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
-#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
+# define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
-#define CH_DBG_TRACE_BUFFER_SIZE 128
+# define CH_DBG_TRACE_BUFFER_SIZE 128
/**
* @brief Debug option, stack checks.
@@ -374,7 +374,7 @@
* @note The default failure mode is to halt the system with the global
* @p panic_msg variable set to @p NULL.
*/
-#define CH_DBG_ENABLE_STACK_CHECK TRUE
+# define CH_DBG_ENABLE_STACK_CHECK TRUE
/**
* @brief Debug option, stacks initialization.
@@ -384,7 +384,7 @@
*
* @note The default is @p FALSE.
*/
-#define CH_DBG_FILL_THREADS FALSE
+# define CH_DBG_FILL_THREADS FALSE
/**
* @brief Debug option, threads profiling.
@@ -395,7 +395,7 @@
* @note This debug option is not currently compatible with the
* tickless mode.
*/
-#define CH_DBG_THREADS_PROFILING FALSE
+# define CH_DBG_THREADS_PROFILING FALSE
/** @} */
@@ -410,8 +410,7 @@
* @brief Threads descriptor structure extension.
* @details User fields added to the end of the @p thread_t structure.
*/
-#define CH_CFG_THREAD_EXTRA_FIELDS \
- /* Add threads custom fields here.*/
+# define CH_CFG_THREAD_EXTRA_FIELDS /* Add threads custom fields here.*/
/**
* @brief Threads initialization hook.
@@ -420,39 +419,34 @@
* @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
-#define CH_CFG_THREAD_INIT_HOOK(tp) { \
- /* Add threads initialization code here.*/ \
-}
+# define CH_CFG_THREAD_INIT_HOOK(tp) \
+ { /* Add threads initialization code here.*/ }
/**
* @brief Threads finalization hook.
* @details User finalization code added to the @p chThdExit() API.
*/
-#define CH_CFG_THREAD_EXIT_HOOK(tp) { \
- /* Add threads finalization code here.*/ \
-}
+# define CH_CFG_THREAD_EXIT_HOOK(tp) \
+ { /* Add threads finalization code here.*/ }
/**
* @brief Context switch hook.
* @details This hook is invoked just before switching between threads.
*/
-#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \
- /* Context switch code here.*/ \
-}
+# define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) \
+ { /* Context switch code here.*/ }
/**
* @brief ISR enter hook.
*/
-#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
- /* IRQ prologue code here.*/ \
-}
+# define CH_CFG_IRQ_PROLOGUE_HOOK() \
+ { /* IRQ prologue code here.*/ }
/**
* @brief ISR exit hook.
*/
-#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
- /* IRQ epilogue code here.*/ \
-}
+# define CH_CFG_IRQ_EPILOGUE_HOOK() \
+ { /* IRQ epilogue code here.*/ }
/**
* @brief Idle thread enter hook.
@@ -460,9 +454,8 @@
* should be invoked from here.
* @note This macro can be used to activate a power saving mode.
*/
-#define CH_CFG_IDLE_ENTER_HOOK() { \
- /* Idle-enter code here.*/ \
-}
+# define CH_CFG_IDLE_ENTER_HOOK() \
+ { /* Idle-enter code here.*/ }
/**
* @brief Idle thread leave hook.
@@ -470,44 +463,39 @@
* should be invoked from here.
* @note This macro can be used to deactivate a power saving mode.
*/
-#define CH_CFG_IDLE_LEAVE_HOOK() { \
- /* Idle-leave code here.*/ \
-}
+# define CH_CFG_IDLE_LEAVE_HOOK() \
+ { /* Idle-leave code here.*/ }
/**
* @brief Idle Loop hook.
* @details This hook is continuously invoked by the idle thread loop.
*/
-#define CH_CFG_IDLE_LOOP_HOOK() { \
- /* Idle loop code here.*/ \
-}
+# define CH_CFG_IDLE_LOOP_HOOK() \
+ { /* Idle loop code here.*/ }
/**
* @brief System tick event hook.
* @details This hook is invoked in the system tick handler immediately
* after processing the virtual timers queue.
*/
-#define CH_CFG_SYSTEM_TICK_HOOK() { \
- /* System tick event code here.*/ \
-}
+# define CH_CFG_SYSTEM_TICK_HOOK() \
+ { /* System tick event code here.*/ }
/**
* @brief System halt hook.
* @details This hook is invoked in case to a system halting error before
* the system is halted.
*/
-#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \
- /* System halt code here.*/ \
-}
+# define CH_CFG_SYSTEM_HALT_HOOK(reason) \
+ { /* System halt code here.*/ }
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
-#define CH_CFG_TRACE_HOOK(tep) { \
- /* Trace code here.*/ \
-}
+# define CH_CFG_TRACE_HOOK(tep) \
+ { /* Trace code here.*/ }
/** @} */
@@ -515,6 +503,6 @@
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
-#endif /* CHCONF_H */
+#endif /* CHCONF_H */
/** @} */
diff --git a/quantum/stm32/halconf.h b/quantum/stm32/halconf.h
index a14ace02b4..72e011d3dc 100644
--- a/quantum/stm32/halconf.h
+++ b/quantum/stm32/halconf.h
@@ -26,156 +26,156 @@
*/
#ifndef HALCONF_H
-#define HALCONF_H
+# define HALCONF_H
-#include "mcuconf.h"
+# include "mcuconf.h"
/**
* @brief Enables the PAL subsystem.
*/
-#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
-#define HAL_USE_PAL TRUE
-#endif
+# if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+# define HAL_USE_PAL TRUE
+# endif
/**
* @brief Enables the ADC subsystem.
*/
-#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
-#define HAL_USE_ADC FALSE
-#endif
+# if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+# define HAL_USE_ADC FALSE
+# endif
/**
* @brief Enables the CAN subsystem.
*/
-#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
-#define HAL_USE_CAN FALSE
-#endif
+# if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+# define HAL_USE_CAN FALSE
+# endif
/**
* @brief Enables the DAC subsystem.
*/
-#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
-#define HAL_USE_DAC TRUE
-#endif
+# if !defined(HAL_USE_DAC) || defined(__DOXYGEN__)
+# define HAL_USE_DAC TRUE
+# endif
/**
* @brief Enables the EXT subsystem.
*/
-#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
-#define HAL_USE_EXT FALSE
-#endif
+# if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+# define HAL_USE_EXT FALSE
+# endif
/**
* @brief Enables the GPT subsystem.
*/
-#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
-#define HAL_USE_GPT TRUE
-#endif
+# if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+# define HAL_USE_GPT TRUE
+# endif
/**
* @brief Enables the I2C subsystem.
*/
-#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
-#define HAL_USE_I2C TRUE
-#endif
+# if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+# define HAL_USE_I2C TRUE
+# endif
/**
* @brief Enables the I2S subsystem.
*/
-#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
-#define HAL_USE_I2S FALSE
-#endif
+# if !defined(HAL_USE_I2S) || defined(__DOXYGEN__)
+# define HAL_USE_I2S FALSE
+# endif
/**
* @brief Enables the ICU subsystem.
*/
-#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
-#define HAL_USE_ICU FALSE
-#endif
+# if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+# define HAL_USE_ICU FALSE
+# endif
/**
* @brief Enables the MAC subsystem.
*/
-#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
-#define HAL_USE_MAC FALSE
-#endif
+# if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+# define HAL_USE_MAC FALSE
+# endif
/**
* @brief Enables the MMC_SPI subsystem.
*/
-#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_MMC_SPI FALSE
-#endif
+# if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+# define HAL_USE_MMC_SPI FALSE
+# endif
/**
* @brief Enables the PWM subsystem.
*/
-#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
-#define HAL_USE_PWM TRUE
-#endif
+# if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+# define HAL_USE_PWM TRUE
+# endif
/**
* @brief Enables the QSPI subsystem.
*/
-#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
-#define HAL_USE_QSPI FALSE
-#endif
+# if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__)
+# define HAL_USE_QSPI FALSE
+# endif
/**
* @brief Enables the RTC subsystem.
*/
-#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
-#define HAL_USE_RTC FALSE
-#endif
+# if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+# define HAL_USE_RTC FALSE
+# endif
/**
* @brief Enables the SDC subsystem.
*/
-#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
-#define HAL_USE_SDC FALSE
-#endif
+# if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+# define HAL_USE_SDC FALSE
+# endif
/**
* @brief Enables the SERIAL subsystem.
*/
-#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL FALSE
-#endif
+# if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+# define HAL_USE_SERIAL FALSE
+# endif
/**
* @brief Enables the SERIAL over USB subsystem.
*/
-#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
-#define HAL_USE_SERIAL_USB TRUE
-#endif
+# if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+# define HAL_USE_SERIAL_USB TRUE
+# endif
/**
* @brief Enables the SPI subsystem.
*/
-#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
-#define HAL_USE_SPI FALSE
-#endif
+# if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+# define HAL_USE_SPI FALSE
+# endif
/**
* @brief Enables the UART subsystem.
*/
-#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
-#define HAL_USE_UART FALSE
-#endif
+# if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+# define HAL_USE_UART FALSE
+# endif
/**
* @brief Enables the USB subsystem.
*/
-#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
-#define HAL_USE_USB TRUE
-#endif
+# if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+# define HAL_USE_USB TRUE
+# endif
/**
* @brief Enables the WDG subsystem.
*/
-#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
-#define HAL_USE_WDG FALSE
-#endif
+# if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
+# define HAL_USE_WDG FALSE
+# endif
/*===========================================================================*/
/* ADC driver related settings. */
@@ -185,17 +185,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
-#define ADC_USE_WAIT TRUE
-#endif
+# if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+# define ADC_USE_WAIT TRUE
+# endif
/**
* @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define ADC_USE_MUTUAL_EXCLUSION TRUE
-#endif
+# if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+# define ADC_USE_MUTUAL_EXCLUSION TRUE
+# endif
/*===========================================================================*/
/* CAN driver related settings. */
@@ -204,9 +204,9 @@
/**
* @brief Sleep mode related APIs inclusion switch.
*/
-#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
-#define CAN_USE_SLEEP_MODE TRUE
-#endif
+# if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+# define CAN_USE_SLEEP_MODE TRUE
+# endif
/*===========================================================================*/
/* I2C driver related settings. */
@@ -215,9 +215,9 @@
/**
* @brief Enables the mutual exclusion APIs on the I2C bus.
*/
-#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define I2C_USE_MUTUAL_EXCLUSION TRUE
-#endif
+# if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+# define I2C_USE_MUTUAL_EXCLUSION TRUE
+# endif
/*===========================================================================*/
/* MAC driver related settings. */
@@ -226,16 +226,16 @@
/**
* @brief Enables an event sources for incoming packets.
*/
-#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
-#define MAC_USE_ZERO_COPY FALSE
-#endif
+# if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__)
+# define MAC_USE_ZERO_COPY FALSE
+# endif
/**
* @brief Enables an event sources for incoming packets.
*/
-#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
-#define MAC_USE_EVENTS TRUE
-#endif
+# if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+# define MAC_USE_EVENTS TRUE
+# endif
/*===========================================================================*/
/* MMC_SPI driver related settings. */
@@ -249,9 +249,9 @@
* This option is recommended also if the SPI driver does not
* use a DMA channel and heavily loads the CPU.
*/
-#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
-#define MMC_NICE_WAITING TRUE
-#endif
+# if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+# define MMC_NICE_WAITING TRUE
+# endif
/*===========================================================================*/
/* SDC driver related settings. */
@@ -261,18 +261,18 @@
* @brief Number of initialization attempts before rejecting the card.
* @note Attempts are performed at 10mS intervals.
*/
-#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
-#define SDC_INIT_RETRY 100
-#endif
+# if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+# define SDC_INIT_RETRY 100
+# endif
/**
* @brief Include support for MMC cards.
* @note MMC support is not yet implemented so this option must be kept
* at @p FALSE.
*/
-#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
-#define SDC_MMC_SUPPORT FALSE
-#endif
+# if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+# define SDC_MMC_SUPPORT FALSE
+# endif
/**
* @brief Delays insertions.
@@ -280,9 +280,9 @@
* routines releasing some extra CPU time for the threads with
* lower priority, this may slow down the driver a bit however.
*/
-#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
-#define SDC_NICE_WAITING TRUE
-#endif
+# if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+# define SDC_NICE_WAITING TRUE
+# endif
/*===========================================================================*/
/* SERIAL driver related settings. */
@@ -293,9 +293,9 @@
* @details Configuration parameter, this is the baud rate selected for the
* default configuration.
*/
-#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
-#define SERIAL_DEFAULT_BITRATE 38400
-#endif
+# if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+# define SERIAL_DEFAULT_BITRATE 38400
+# endif
/**
* @brief Serial buffers size.
@@ -304,9 +304,9 @@
* @note The default is 16 bytes for both the transmission and receive
* buffers.
*/
-#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_BUFFERS_SIZE 16
-#endif
+# if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+# define SERIAL_BUFFERS_SIZE 16
+# endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
@@ -319,17 +319,17 @@
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
-#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
-#define SERIAL_USB_BUFFERS_SIZE 1
-#endif
+# if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
+# define SERIAL_USB_BUFFERS_SIZE 1
+# endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
-#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
-#define SERIAL_USB_BUFFERS_NUMBER 2
-#endif
+# if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
+# define SERIAL_USB_BUFFERS_NUMBER 2
+# endif
/*===========================================================================*/
/* SPI driver related settings. */
@@ -339,17 +339,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
-#define SPI_USE_WAIT TRUE
-#endif
+# if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+# define SPI_USE_WAIT TRUE
+# endif
/**
* @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define SPI_USE_MUTUAL_EXCLUSION TRUE
-#endif
+# if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+# define SPI_USE_MUTUAL_EXCLUSION TRUE
+# endif
/*===========================================================================*/
/* UART driver related settings. */
@@ -359,17 +359,17 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
-#define UART_USE_WAIT FALSE
-#endif
+# if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
+# define UART_USE_WAIT FALSE
+# endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
-#define UART_USE_MUTUAL_EXCLUSION FALSE
-#endif
+# if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+# define UART_USE_MUTUAL_EXCLUSION FALSE
+# endif
/*===========================================================================*/
/* USB driver related settings. */
@@ -379,9 +379,9 @@
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
-#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
-#define USB_USE_WAIT TRUE
-#endif
+# if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
+# define USB_USE_WAIT TRUE
+# endif
#endif /* HALCONF_H */
diff --git a/quantum/stm32/mcuconf.h b/quantum/stm32/mcuconf.h
index e16426bbdf..23c9610b57 100644
--- a/quantum/stm32/mcuconf.h
+++ b/quantum/stm32/mcuconf.h
@@ -36,35 +36,35 @@
/*
* HAL driver system settings.
*/
-#define STM32_NO_INIT FALSE
-#define STM32_PVD_ENABLE FALSE
-#define STM32_PLS STM32_PLS_LEV0
-#define STM32_HSI_ENABLED TRUE
-#define STM32_LSI_ENABLED TRUE
-#define STM32_HSE_ENABLED TRUE
-#define STM32_LSE_ENABLED FALSE
-#define STM32_SW STM32_SW_PLL
-#define STM32_PLLSRC STM32_PLLSRC_HSE
-#define STM32_PREDIV_VALUE 1
-#define STM32_PLLMUL_VALUE 9
-#define STM32_HPRE STM32_HPRE_DIV1
-#define STM32_PPRE1 STM32_PPRE1_DIV2
-#define STM32_PPRE2 STM32_PPRE2_DIV2
-#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
-#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
-#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
-#define STM32_USART1SW STM32_USART1SW_PCLK
-#define STM32_USART2SW STM32_USART2SW_PCLK
-#define STM32_USART3SW STM32_USART3SW_PCLK
-#define STM32_UART4SW STM32_UART4SW_PCLK
-#define STM32_UART5SW STM32_UART5SW_PCLK
-#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
-#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
-#define STM32_TIM1SW STM32_TIM1SW_PCLK2
-#define STM32_TIM8SW STM32_TIM8SW_PCLK2
-#define STM32_RTCSEL STM32_RTCSEL_LSI
-#define STM32_USB_CLOCK_REQUIRED TRUE
-#define STM32_USBPRE STM32_USBPRE_DIV1P5
+#define STM32_NO_INIT FALSE
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PREDIV_VALUE 1
+#define STM32_PLLMUL_VALUE 9
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV2
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
+#define STM32_ADC12PRES STM32_ADC12PRES_DIV1
+#define STM32_ADC34PRES STM32_ADC34PRES_DIV1
+#define STM32_USART1SW STM32_USART1SW_PCLK
+#define STM32_USART2SW STM32_USART2SW_PCLK
+#define STM32_USART3SW STM32_USART3SW_PCLK
+#define STM32_UART4SW STM32_UART4SW_PCLK
+#define STM32_UART5SW STM32_UART5SW_PCLK
+#define STM32_I2C1SW STM32_I2C1SW_SYSCLK
+#define STM32_I2C2SW STM32_I2C2SW_SYSCLK
+#define STM32_TIM1SW STM32_TIM1SW_PCLK2
+#define STM32_TIM8SW STM32_TIM8SW_PCLK2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_USB_CLOCK_REQUIRED TRUE
+#define STM32_USBPRE STM32_USBPRE_DIV1P5
#undef STM32_HSE_BYPASS
// #error "oh no"
@@ -73,185 +73,185 @@
/*
* ADC driver system settings.
*/
-#define STM32_ADC_DUAL_MODE FALSE
-#define STM32_ADC_COMPACT_SAMPLES FALSE
-#define STM32_ADC_USE_ADC1 FALSE
-#define STM32_ADC_USE_ADC2 FALSE
-#define STM32_ADC_USE_ADC3 FALSE
-#define STM32_ADC_USE_ADC4 FALSE
-#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
-#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
-#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
-#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
-#define STM32_ADC_ADC1_DMA_PRIORITY 2
-#define STM32_ADC_ADC2_DMA_PRIORITY 2
-#define STM32_ADC_ADC3_DMA_PRIORITY 2
-#define STM32_ADC_ADC4_DMA_PRIORITY 2
-#define STM32_ADC_ADC12_IRQ_PRIORITY 5
-#define STM32_ADC_ADC3_IRQ_PRIORITY 5
-#define STM32_ADC_ADC4_IRQ_PRIORITY 5
-#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
-#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_COMPACT_SAMPLES FALSE
+#define STM32_ADC_USE_ADC1 FALSE
+#define STM32_ADC_USE_ADC2 FALSE
+#define STM32_ADC_USE_ADC3 FALSE
+#define STM32_ADC_USE_ADC4 FALSE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC4_DMA_PRIORITY 2
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
/*
* CAN driver system settings.
*/
-#define STM32_CAN_USE_CAN1 FALSE
-#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+#define STM32_CAN_USE_CAN1 FALSE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
-#define STM32_DAC_DUAL_MODE FALSE
-#define STM32_DAC_USE_DAC1_CH1 TRUE
-#define STM32_DAC_USE_DAC1_CH2 TRUE
-#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
-#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
-#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
-#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 TRUE
+#define STM32_DAC_USE_DAC1_CH2 TRUE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
/*
* EXT driver system settings.
*/
-#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
-#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI30_32_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI33_IRQ_PRIORITY 6
/*
* GPT driver system settings.
*/
-#define STM32_GPT_USE_TIM1 FALSE
-#define STM32_GPT_USE_TIM2 FALSE
-#define STM32_GPT_USE_TIM3 FALSE
-#define STM32_GPT_USE_TIM4 FALSE
-#define STM32_GPT_USE_TIM6 TRUE
-#define STM32_GPT_USE_TIM7 TRUE
-#define STM32_GPT_USE_TIM8 TRUE
-#define STM32_GPT_TIM1_IRQ_PRIORITY 7
-#define STM32_GPT_TIM2_IRQ_PRIORITY 7
-#define STM32_GPT_TIM3_IRQ_PRIORITY 7
-#define STM32_GPT_TIM4_IRQ_PRIORITY 7
-#define STM32_GPT_TIM6_IRQ_PRIORITY 7
-#define STM32_GPT_TIM7_IRQ_PRIORITY 7
-#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM6 TRUE
+#define STM32_GPT_USE_TIM7 TRUE
+#define STM32_GPT_USE_TIM8 TRUE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM6_IRQ_PRIORITY 7
+#define STM32_GPT_TIM7_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
-#define STM32_I2C_USE_I2C1 TRUE
-#define STM32_I2C_USE_I2C2 FALSE
-#define STM32_I2C_BUSY_TIMEOUT 50
-#define STM32_I2C_I2C1_IRQ_PRIORITY 10
-#define STM32_I2C_I2C2_IRQ_PRIORITY 10
-#define STM32_I2C_USE_DMA TRUE
-#define STM32_I2C_I2C1_DMA_PRIORITY 1
-#define STM32_I2C_I2C2_DMA_PRIORITY 1
-#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+#define STM32_I2C_USE_I2C1 TRUE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_BUSY_TIMEOUT 50
+#define STM32_I2C_I2C1_IRQ_PRIORITY 10
+#define STM32_I2C_I2C2_IRQ_PRIORITY 10
+#define STM32_I2C_USE_DMA TRUE
+#define STM32_I2C_I2C1_DMA_PRIORITY 1
+#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
-#define STM32_ICU_USE_TIM1 FALSE
-#define STM32_ICU_USE_TIM2 FALSE
-#define STM32_ICU_USE_TIM3 FALSE
-#define STM32_ICU_USE_TIM4 FALSE
-#define STM32_ICU_USE_TIM8 FALSE
-#define STM32_ICU_TIM1_IRQ_PRIORITY 7
-#define STM32_ICU_TIM2_IRQ_PRIORITY 7
-#define STM32_ICU_TIM3_IRQ_PRIORITY 7
-#define STM32_ICU_TIM4_IRQ_PRIORITY 7
-#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* PWM driver system settings.
*/
-#define STM32_PWM_USE_ADVANCED FALSE
-#define STM32_PWM_USE_TIM1 FALSE
-#define STM32_PWM_USE_TIM2 TRUE
-#define STM32_PWM_USE_TIM3 TRUE
-#define STM32_PWM_USE_TIM4 TRUE
-#define STM32_PWM_USE_TIM8 FALSE
-#define STM32_PWM_TIM1_IRQ_PRIORITY 7
-#define STM32_PWM_TIM2_IRQ_PRIORITY 7
-#define STM32_PWM_TIM3_IRQ_PRIORITY 7
-#define STM32_PWM_TIM4_IRQ_PRIORITY 7
-#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 TRUE
+#define STM32_PWM_USE_TIM3 TRUE
+#define STM32_PWM_USE_TIM4 TRUE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
-#define STM32_SERIAL_USE_USART1 FALSE
-#define STM32_SERIAL_USE_USART2 TRUE
-#define STM32_SERIAL_USE_USART3 FALSE
-#define STM32_SERIAL_USE_UART4 FALSE
-#define STM32_SERIAL_USE_UART5 FALSE
-#define STM32_SERIAL_USART1_PRIORITY 12
-#define STM32_SERIAL_USART2_PRIORITY 12
-#define STM32_SERIAL_USART3_PRIORITY 12
-#define STM32_SERIAL_UART4_PRIORITY 12
-#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
/*
* SPI driver system settings.
*/
-#define STM32_SPI_USE_SPI1 FALSE
-#define STM32_SPI_USE_SPI2 FALSE
-#define STM32_SPI_USE_SPI3 FALSE
-#define STM32_SPI_SPI1_DMA_PRIORITY 1
-#define STM32_SPI_SPI2_DMA_PRIORITY 1
-#define STM32_SPI_SPI3_DMA_PRIORITY 1
-#define STM32_SPI_SPI1_IRQ_PRIORITY 10
-#define STM32_SPI_SPI2_IRQ_PRIORITY 10
-#define STM32_SPI_SPI3_IRQ_PRIORITY 10
-#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+#define STM32_SPI_USE_SPI1 FALSE
+#define STM32_SPI_USE_SPI2 FALSE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
-#define STM32_ST_IRQ_PRIORITY 8
-#define STM32_ST_USE_TIMER 2
+#define STM32_ST_IRQ_PRIORITY 8
+#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
-#define STM32_UART_USE_USART1 FALSE
-#define STM32_UART_USE_USART2 FALSE
-#define STM32_UART_USE_USART3 FALSE
-#define STM32_UART_USART1_IRQ_PRIORITY 12
-#define STM32_UART_USART2_IRQ_PRIORITY 12
-#define STM32_UART_USART3_IRQ_PRIORITY 12
-#define STM32_UART_USART1_DMA_PRIORITY 0
-#define STM32_UART_USART2_DMA_PRIORITY 0
-#define STM32_UART_USART3_DMA_PRIORITY 0
-#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
-#define STM32_USB_USE_USB1 TRUE
-#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
-#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
-#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
+#define STM32_USB_USE_USB1 TRUE
+#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
+#define STM32_USB_USB1_HP_IRQ_PRIORITY 13
+#define STM32_USB_USB1_LP_IRQ_PRIORITY 14
/*
* WDG driver system settings.
*/
-#define STM32_WDG_USE_IWDG FALSE
+#define STM32_WDG_USE_IWDG FALSE
#endif /* MCUCONF_H */