summaryrefslogtreecommitdiff
path: root/platforms/chibios
diff options
context:
space:
mode:
authorJoy Lee <joylee.lc@foxmail.com>2022-08-14 09:21:46 +0800
committerGitHub <noreply@github.com>2022-08-13 18:21:46 -0700
commitc02d7ae86f5bc24f7f6201eccf09acec3d2879cf (patch)
treed00b1c3dd3d51006e743c3e357df46fde886c389 /platforms/chibios
parent6b1c7d20aadf40655585df465c4680eca5eca7ae (diff)
Added ws2812_pwm support for WB32 MCU. (#17142)
Co-authored-by: Joy <chang.li@westberrytech.com>
Diffstat (limited to 'platforms/chibios')
-rw-r--r--platforms/chibios/drivers/ws2812_pwm.c27
1 files changed, 23 insertions, 4 deletions
diff --git a/platforms/chibios/drivers/ws2812_pwm.c b/platforms/chibios/drivers/ws2812_pwm.c
index 57187676d7..37c613049f 100644
--- a/platforms/chibios/drivers/ws2812_pwm.c
+++ b/platforms/chibios/drivers/ws2812_pwm.c
@@ -17,13 +17,25 @@
# define WS2812_PWM_CHANNEL 2 // Channel
#endif
#ifndef WS2812_PWM_PAL_MODE
-# define WS2812_PWM_PAL_MODE 2 // DI Pin's alternate function value
+# if defined(WB32F3G71xx) || defined(WB32FQ95xx)
+# define WS2812_PWM_PAL_MODE 1 // DI Pin's alternate function value
+# else
+# define WS2812_PWM_PAL_MODE 2 // DI Pin's alternate function value
+# endif
#endif
#ifndef WS2812_DMA_STREAM
-# define WS2812_DMA_STREAM STM32_DMA1_STREAM2 // DMA Stream for TIMx_UP
+# if defined(WB32F3G71xx) || defined(WB32FQ95xx)
+# define WS2812_DMA_STREAM WB32_DMA1_STREAM1 // DMA Stream for TIMx_UP
+# else
+# define WS2812_DMA_STREAM STM32_DMA1_STREAM2 // DMA Stream for TIMx_UP
+# endif
#endif
#ifndef WS2812_DMA_CHANNEL
-# define WS2812_DMA_CHANNEL 2 // DMA Channel for TIMx_UP
+# if defined(WB32F3G71xx) || defined(WB32FQ95xx)
+# define WS2812_DMA_CHANNEL WB32_DMAC_HWHIF_TIM2_UP // DMA Channel for TIM2_UP
+# else
+# define WS2812_DMA_CHANNEL 2 // DMA Channel for TIMx_UP
+# endif
#endif
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE) && !defined(WS2812_DMAMUX_ID)
# error "please consult your MCU's datasheet and specify in your config.h: #define WS2812_DMAMUX_ID STM32_DMAMUX1_TIM?_UP"
@@ -284,11 +296,18 @@ void ws2812_init(void) {
// Configure DMA
// dmaInit(); // Joe added this
+#if defined(WB32F3G71xx) || defined(WB32FQ95xx)
+ dmaStreamAlloc(WS2812_DMA_STREAM - WB32_DMA_STREAM(0), 10, NULL, NULL);
+ dmaStreamSetSource(WS2812_DMA_STREAM, ws2812_frame_buffer);
+ dmaStreamSetDestination(WS2812_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
+ dmaStreamSetMode(WS2812_DMA_STREAM, WB32_DMA_CHCFG_HWHIF(WS2812_DMA_CHANNEL) | WB32_DMA_CHCFG_DIR_M2P | WB32_DMA_CHCFG_PSIZE_WORD | WB32_DMA_CHCFG_MSIZE_WORD | WB32_DMA_CHCFG_MINC | WB32_DMA_CHCFG_CIRC | WB32_DMA_CHCFG_TCIE | WB32_DMA_CHCFG_PL(3));
+#else
dmaStreamAlloc(WS2812_DMA_STREAM - STM32_DMA_STREAM(0), 10, NULL, NULL);
dmaStreamSetPeripheral(WS2812_DMA_STREAM, &(WS2812_PWM_DRIVER.tim->CCR[WS2812_PWM_CHANNEL - 1])); // Ziel ist der An-Zeit im Cap-Comp-Register
dmaStreamSetMemory0(WS2812_DMA_STREAM, ws2812_frame_buffer);
- dmaStreamSetTransactionSize(WS2812_DMA_STREAM, WS2812_BIT_N);
dmaStreamSetMode(WS2812_DMA_STREAM, STM32_DMA_CR_CHSEL(WS2812_DMA_CHANNEL) | STM32_DMA_CR_DIR_M2P | STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_MINC | STM32_DMA_CR_CIRC | STM32_DMA_CR_PL(3));
+#endif
+ dmaStreamSetTransactionSize(WS2812_DMA_STREAM, WS2812_BIT_N);
// M2P: Memory 2 Periph; PL: Priority Level
#if (STM32_DMA_SUPPORTS_DMAMUX == TRUE)