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| author | Drashna Jael're <drashna@live.com> | 2022-11-08 17:14:27 -0800 |
|---|---|---|
| committer | Drashna Jael're <drashna@live.com> | 2022-11-08 17:14:27 -0800 |
| commit | 64f04b30c2f48fc0e7c49ca043443f03dc56df94 (patch) | |
| tree | e0f374d3b92bacefd22c31e7bda8ee1c6fcb37de /platforms/chibios/gd32v_compatibility.h | |
| parent | d9f575fa86ca10b990958d4e677c6a0a387dc7c3 (diff) | |
| parent | 96c48a5f4aa461ed31fd4ee61151ac206e16fb5f (diff) | |
Merge tag '0.18.16' into firmware22
Diffstat (limited to 'platforms/chibios/gd32v_compatibility.h')
| -rw-r--r-- | platforms/chibios/gd32v_compatibility.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/platforms/chibios/gd32v_compatibility.h b/platforms/chibios/gd32v_compatibility.h index a3148fb6d2..d01c3d00a2 100644 --- a/platforms/chibios/gd32v_compatibility.h +++ b/platforms/chibios/gd32v_compatibility.h @@ -35,7 +35,9 @@ #define STM32_DMA_STREAM_ID(peripheral, channel) GD32_DMA_STREAM_ID(peripheral - 1, channel - 1) #define STM32_DMA_CR_DIR_M2P GD32_DMA_CTL_DIR_M2P #define STM32_DMA_CR_PSIZE_WORD GD32_DMA_CTL_PWIDTH_WORD +#define STM32_DMA_CR_PSIZE_HWORD GD32_DMA_CTL_PWIDTH_HWORD #define STM32_DMA_CR_MSIZE_WORD GD32_DMA_CTL_MWIDTH_WORD +#define STM32_DMA_CR_MSIZE_BYTE GD32_DMA_CTL_MWIDTH_BYTE #define STM32_DMA_CR_MINC GD32_DMA_CTL_MNAGA #define STM32_DMA_CR_CIRC GD32_DMA_CTL_CMEN #define STM32_DMA_CR_PL GD32_DMA_CTL_PRIO |