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authorJoy Lee <chang.li@westberrytech.com>2021-11-27 06:28:18 +0800
committerGitHub <noreply@github.com>2021-11-27 09:28:18 +1100
commit68838bb700413144c6fdaf680f3d412b8231b584 (patch)
tree771e7fea9bc145c9e833ac66dcb712af9b55e532 /platforms/chibios/drivers/spi_master.c
parentb04f66f2452494206673323c9495ea6a56c0cb06 (diff)
Westberrytech pr (#14422)
* Added support for WB32 MCU * Modified eeprom_wb32.c * Remove the eeprom_wb32-related code
Diffstat (limited to 'platforms/chibios/drivers/spi_master.c')
-rw-r--r--platforms/chibios/drivers/spi_master.c33
1 files changed, 33 insertions, 0 deletions
diff --git a/platforms/chibios/drivers/spi_master.c b/platforms/chibios/drivers/spi_master.c
index c592369dde..dde0bb0597 100644
--- a/platforms/chibios/drivers/spi_master.c
+++ b/platforms/chibios/drivers/spi_master.c
@@ -54,6 +54,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
return false;
}
+#ifndef WB32F3G71xx
uint16_t roundedDivisor = 2;
while (roundedDivisor < divisor) {
roundedDivisor <<= 1;
@@ -62,6 +63,7 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
if (roundedDivisor < 2 || roundedDivisor > 256) {
return false;
}
+#endif
#if defined(K20x) || defined(KL2x)
spiConfig.tar0 = SPIx_CTARn_FMSZ(7) | SPIx_CTARn_ASC(1);
@@ -135,6 +137,37 @@ bool spi_start(pin_t slavePin, bool lsbFirst, uint8_t mode, uint16_t divisor) {
}
spiConfig.cpr = (roundedDivisor - 1) >> 1;
+
+#elif defined(WB32F3G71xx)
+ if (!lsbFirst) {
+ osalDbgAssert(lsbFirst != FALSE, "unsupported lsbFirst");
+ }
+
+ if (divisor < 1) {
+ return false;
+ }
+
+ spiConfig.SPI_BaudRatePrescaler = (divisor << 2);
+
+ switch (mode) {
+ case 0:
+ spiConfig.SPI_CPHA = SPI_CPHA_1Edge;
+ spiConfig.SPI_CPOL = SPI_CPOL_Low;
+ break;
+ case 1:
+ spiConfig.SPI_CPHA = SPI_CPHA_2Edge;
+ spiConfig.SPI_CPOL = SPI_CPOL_Low;
+ break;
+ case 2:
+ spiConfig.SPI_CPHA = SPI_CPHA_1Edge;
+ spiConfig.SPI_CPOL = SPI_CPOL_High;
+ break;
+ case 3:
+ spiConfig.SPI_CPHA = SPI_CPHA_2Edge;
+ spiConfig.SPI_CPOL = SPI_CPOL_High;
+ break;
+ }
+
#else
spiConfig.cr1 = 0;