summaryrefslogtreecommitdiff
path: root/platforms/chibios/drivers/i2c_master.c
diff options
context:
space:
mode:
authorzvecr <git@zvecr.com>2022-02-25 23:45:40 +0000
committerzvecr <git@zvecr.com>2022-02-25 23:45:40 +0000
commite7931289918221081cbe2a7ea5df27a5d86324db (patch)
tree0b06145520f8aaf5ff5cb928aa5176fc2dd23619 /platforms/chibios/drivers/i2c_master.c
parentc0ee3d2c79388187883b1b1b1d1a0b6842acf741 (diff)
parentcf31355f08dca311a013168eb3eb995e2fc6a3d1 (diff)
Merge remote-tracking branch 'origin/develop'
Diffstat (limited to 'platforms/chibios/drivers/i2c_master.c')
-rw-r--r--platforms/chibios/drivers/i2c_master.c63
1 files changed, 62 insertions, 1 deletions
diff --git a/platforms/chibios/drivers/i2c_master.c b/platforms/chibios/drivers/i2c_master.c
index 43591d56f8..d10bdbabc1 100644
--- a/platforms/chibios/drivers/i2c_master.c
+++ b/platforms/chibios/drivers/i2c_master.c
@@ -27,8 +27,67 @@
#include "quantum.h"
#include "i2c_master.h"
#include <string.h>
+#include <ch.h>
#include <hal.h>
+#ifndef I2C1_SCL_PIN
+# define I2C1_SCL_PIN B6
+#endif
+#ifndef I2C1_SDA_PIN
+# define I2C1_SDA_PIN B7
+#endif
+
+#ifdef USE_I2CV1
+# ifndef I2C1_OPMODE
+# define I2C1_OPMODE OPMODE_I2C
+# endif
+# ifndef I2C1_CLOCK_SPEED
+# define I2C1_CLOCK_SPEED 100000 /* 400000 */
+# endif
+# ifndef I2C1_DUTY_CYCLE
+# define I2C1_DUTY_CYCLE STD_DUTY_CYCLE /* FAST_DUTY_CYCLE_2 */
+# endif
+#else
+// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
+// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
+# ifndef I2C1_TIMINGR_PRESC
+# define I2C1_TIMINGR_PRESC 0U
+# endif
+# ifndef I2C1_TIMINGR_SCLDEL
+# define I2C1_TIMINGR_SCLDEL 7U
+# endif
+# ifndef I2C1_TIMINGR_SDADEL
+# define I2C1_TIMINGR_SDADEL 0U
+# endif
+# ifndef I2C1_TIMINGR_SCLH
+# define I2C1_TIMINGR_SCLH 38U
+# endif
+# ifndef I2C1_TIMINGR_SCLL
+# define I2C1_TIMINGR_SCLL 129U
+# endif
+#endif
+
+#ifndef I2C_DRIVER
+# define I2C_DRIVER I2CD1
+#endif
+
+#ifdef USE_GPIOV1
+# ifndef I2C1_SCL_PAL_MODE
+# define I2C1_SCL_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
+# endif
+# ifndef I2C1_SDA_PAL_MODE
+# define I2C1_SDA_PAL_MODE PAL_MODE_ALTERNATE_OPENDRAIN
+# endif
+#else
+// The default PAL alternate modes are used to signal that the pins are used for I2C
+# ifndef I2C1_SCL_PAL_MODE
+# define I2C1_SCL_PAL_MODE 4
+# endif
+# ifndef I2C1_SDA_PAL_MODE
+# define I2C1_SDA_PAL_MODE 4
+# endif
+#endif
+
static uint8_t i2c_address;
static const I2CConfig i2cconfig = {
@@ -144,4 +203,6 @@ i2c_status_t i2c_readReg16(uint8_t devaddr, uint16_t regaddr, uint8_t* data, uin
return chibios_to_qmk(&status);
}
-void i2c_stop(void) { i2cStop(&I2C_DRIVER); }
+void i2c_stop(void) {
+ i2cStop(&I2C_DRIVER);
+}