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authorDrashna Jaelre <drashna@live.com>2022-01-30 13:20:33 -0800
committerGitHub <noreply@github.com>2022-01-30 13:20:33 -0800
commit941b1d35b8e40a9c93301a1131ef3f3336fee0b5 (patch)
tree54c8d1ec131d5c8a6e0dd89364a9840b3925fcdd /keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h
parent3555ee0555c8a9ff8aea2a101ae02a72b0e76076 (diff)
[Keymap] Add oled improvements and cnano keymap for drashna (#16133)
Diffstat (limited to 'keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h')
-rw-r--r--keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h55
1 files changed, 55 insertions, 0 deletions
diff --git a/keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h b/keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h
new file mode 100644
index 0000000000..d868eae48e
--- /dev/null
+++ b/keyboards/bastardkb/charybdis/3x5/keymaps/drashna/mcuconf.h
@@ -0,0 +1,55 @@
+/* Copyright 2020 Nick Brassel (tzarc)
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <https://www.gnu.org/licenses/>.
+ */
+
+#pragma once
+
+#include_next "mcuconf.h"
+
+#undef STM32_I2C_USE_I2C1
+#define STM32_I2C_USE_I2C1 TRUE
+
+#undef STM32_I2C_I2C1_RX_DMA_STREAM
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#undef STM32_I2C_I2C1_TX_DMA_STREAM
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+
+#undef STM32_PWM_USE_TIM2
+#define STM32_PWM_USE_TIM2 TRUE
+
+#undef STM32_PWM_USE_TIM3
+#define STM32_PWM_USE_TIM3 TRUE
+
+#undef STM32_SPI_USE_SPI1
+#define STM32_SPI_USE_SPI1 TRUE
+
+#undef STM32_SPI_SPI1_RX_DMA_STREAM
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#undef STM32_SPI_SPI1_TX_DMA_STREAM
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+
+#undef STM32_SERIAL_USE_USART2
+#define STM32_SERIAL_USE_USART2 TRUE
+
+#undef STM32_UART_USART2_RX_DMA_STREAM
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#undef STM32_UART_USART2_TX_DMA_STREAM
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+
+#undef STM32_GPT_USE_TIM4
+#define STM32_GPT_USE_TIM4 TRUE
+
+#undef STM32_ST_USE_TIMER
+#define STM32_ST_USE_TIMER 5