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authorNick Brassel <nick@tzarc.org>2021-06-18 09:10:06 +1000
committerGitHub <noreply@github.com>2021-06-18 09:10:06 +1000
commit172e6a703041363decd6fc829542f33180c13beb (patch)
treea5d4afaa672ab44826865fd76b201e3899083192 /drivers/avr/i2c_master.c
parentef92c9ee2cf4745637635ec1895399e4f013914c (diff)
Extensible split data sync (#11930)
* Extensible split data sync capability through transactions. - Split common transport has been split up between the transport layer and data layer. - Split "transactions" model used, with convergence between I2C and serial data definitions. - Slave matrix "generation count" is used to determine if the full slave matrix needs to be retrieved. - Encoders get the same "generation count" treatment. - All other blocks of data are synchronised when a change is detected. - All transmissions have a globally-configurable deadline before a transmission is forced (`FORCED_SYNC_THROTTLE_MS`, default 100ms). - Added atomicity for all core-synced data, preventing partial updates - Added retries to AVR i2c_master's i2c_start, to minimise the number of failed transactions when interrupts are disabled on the slave due to atomicity checks. - Some keyboards have had slight modifications made in order to ensure that they still build due to firmware size restrictions. * Fixup LED_MATRIX compile. * Parameterise ERROR_DISCONNECT_COUNT.
Diffstat (limited to 'drivers/avr/i2c_master.c')
-rw-r--r--drivers/avr/i2c_master.c19
1 files changed, 18 insertions, 1 deletions
diff --git a/drivers/avr/i2c_master.c b/drivers/avr/i2c_master.c
index b1e4885298..2773e00778 100644
--- a/drivers/avr/i2c_master.c
+++ b/drivers/avr/i2c_master.c
@@ -28,8 +28,14 @@
# define F_SCL 400000UL // SCL frequency
#endif
+#ifndef I2C_START_RETRY_COUNT
+# define I2C_START_RETRY_COUNT 20
+#endif // I2C_START_RETRY_COUNT
+
#define TWBR_val (((F_CPU / F_SCL) - 16) / 2)
+#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
+
void i2c_init(void) {
TWSR = 0; /* no prescaler */
TWBR = (uint8_t)TWBR_val;
@@ -47,7 +53,7 @@ void i2c_init(void) {
#endif
}
-i2c_status_t i2c_start(uint8_t address, uint16_t timeout) {
+static i2c_status_t i2c_start_impl(uint8_t address, uint16_t timeout) {
// reset TWI control register
TWCR = 0;
// transmit START condition
@@ -86,6 +92,17 @@ i2c_status_t i2c_start(uint8_t address, uint16_t timeout) {
return I2C_STATUS_SUCCESS;
}
+i2c_status_t i2c_start(uint8_t address, uint16_t timeout) {
+ // Retry i2c_start_impl a bunch times in case the remote side has interrupts disabled.
+ uint16_t timeout_timer = timer_read();
+ uint16_t time_slice = MAX(1, (timeout == (I2C_TIMEOUT_INFINITE)) ? 5 : (timeout / (I2C_START_RETRY_COUNT))); // if it's infinite, wait 1ms between attempts, otherwise split up the entire timeout into the number of retries
+ i2c_status_t status;
+ do {
+ status = i2c_start_impl(address, time_slice);
+ } while ((status < 0) && ((timeout == I2C_TIMEOUT_INFINITE) || (timer_elapsed(timeout_timer) < timeout)));
+ return status;
+}
+
i2c_status_t i2c_write(uint8_t data, uint16_t timeout) {
// load data into data register
TWDR = data;