summaryrefslogtreecommitdiff
path: root/drivers/arm
diff options
context:
space:
mode:
authoryiancar <yiangosyiangou@cytanet.com.cy>2019-10-31 16:19:57 +0000
committerYan-Fa Li <yanfali@gmail.com>2019-10-31 09:19:57 -0700
commit1acafc94f40154db009d5ed55bca204c2399c0a8 (patch)
tree0d0586340850d392ab59b30d806684386914fd93 /drivers/arm
parent2ce6adff2b0b4f049b3bd8b4169cda977c057fa5 (diff)
Correct ARM STM32 I2C frequency. (#7080)
It was beleaved that this setting result in a 400Khz I2C bus. This was incorrect, actual frequency measure with a logic analyzer was around 150Khz. This is derived from the excel sheet linked in the .h file. Also confirmed with the ST IDE.
Diffstat (limited to 'drivers/arm')
-rw-r--r--drivers/arm/i2c_master.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h
index b40fa0a910..a8ed66403a 100644
--- a/drivers/arm/i2c_master.h
+++ b/drivers/arm/i2c_master.h
@@ -73,19 +73,19 @@
// The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock
// For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html
# ifndef I2C1_TIMINGR_PRESC
-# define I2C1_TIMINGR_PRESC 15U
+# define I2C1_TIMINGR_PRESC 0U
# endif
# ifndef I2C1_TIMINGR_SCLDEL
-# define I2C1_TIMINGR_SCLDEL 4U
+# define I2C1_TIMINGR_SCLDEL 7U
# endif
# ifndef I2C1_TIMINGR_SDADEL
-# define I2C1_TIMINGR_SDADEL 2U
+# define I2C1_TIMINGR_SDADEL 0U
# endif
# ifndef I2C1_TIMINGR_SCLH
-# define I2C1_TIMINGR_SCLH 15U
+# define I2C1_TIMINGR_SCLH 38U
# endif
# ifndef I2C1_TIMINGR_SCLL
-# define I2C1_TIMINGR_SCLL 21U
+# define I2C1_TIMINGR_SCLL 129U
# endif
#endif