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| author | yiancar <yiangosyiangou@cytanet.com.cy> | 2019-10-31 16:19:57 +0000 |
|---|---|---|
| committer | Florian Didron <fdidron@users.noreply.github.com> | 2020-01-09 08:57:11 +0900 |
| commit | 619d2ffcb61b0a5c51e9c5ca6aac463a213d3d63 (patch) | |
| tree | 21fac6c67791522e50e30e01c9056d4f956c31eb | |
| parent | 72f42d8e52445127d1ddac39ebbd4ab80ed4b5d2 (diff) | |
Correct ARM STM32 I2C frequency. (#7080)
It was beleaved that this setting result in a 400Khz I2C bus.
This was incorrect, actual frequency measure with a logic analyzer was around 150Khz.
This is derived from the excel sheet linked in the .h file.
Also confirmed with the ST IDE.
| -rw-r--r-- | drivers/arm/i2c_master.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/arm/i2c_master.h b/drivers/arm/i2c_master.h index b40fa0a910..a8ed66403a 100644 --- a/drivers/arm/i2c_master.h +++ b/drivers/arm/i2c_master.h @@ -73,19 +73,19 @@ // The default timing values below configures the I2C clock to 400khz assuming a 72Mhz clock // For more info : https://www.st.com/en/embedded-software/stsw-stm32126.html # ifndef I2C1_TIMINGR_PRESC -# define I2C1_TIMINGR_PRESC 15U +# define I2C1_TIMINGR_PRESC 0U # endif # ifndef I2C1_TIMINGR_SCLDEL -# define I2C1_TIMINGR_SCLDEL 4U +# define I2C1_TIMINGR_SCLDEL 7U # endif # ifndef I2C1_TIMINGR_SDADEL -# define I2C1_TIMINGR_SDADEL 2U +# define I2C1_TIMINGR_SDADEL 0U # endif # ifndef I2C1_TIMINGR_SCLH -# define I2C1_TIMINGR_SCLH 15U +# define I2C1_TIMINGR_SCLH 38U # endif # ifndef I2C1_TIMINGR_SCLL -# define I2C1_TIMINGR_SCLL 21U +# define I2C1_TIMINGR_SCLL 129U # endif #endif |