From 93f6749e06b70ba81e15f8b77e5a18675dacddfe Mon Sep 17 00:00:00 2001 From: skullY Date: Fri, 30 Aug 2019 11:19:03 -0700 Subject: clang-format changes --- tmk_core/protocol/arm_atsam/adc.c | 110 ++++++++++++++++++++++---------------- 1 file changed, 63 insertions(+), 47 deletions(-) (limited to 'tmk_core/protocol/arm_atsam/adc.c') diff --git a/tmk_core/protocol/arm_atsam/adc.c b/tmk_core/protocol/arm_atsam/adc.c index cb5c349b73..1ef1b11d57 100644 --- a/tmk_core/protocol/arm_atsam/adc.c +++ b/tmk_core/protocol/arm_atsam/adc.c @@ -24,76 +24,92 @@ uint16_t v_con_2; uint16_t v_con_1_boot; uint16_t v_con_2_boot; -void ADC0_clock_init(void) -{ +void ADC0_clock_init(void) { DBGC(DC_ADC0_CLOCK_INIT_BEGIN); - MCLK->APBDMASK.bit.ADC0_ = 1; //ADC0 Clock Enable + MCLK->APBDMASK.bit.ADC0_ = 1; // ADC0 Clock Enable - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; //Select generator clock - GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; //Enable peripheral clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.GEN = GEN_OSC0; // Select generator clock + GCLK->PCHCTRL[ADC0_GCLK_ID].bit.CHEN = 1; // Enable peripheral clock DBGC(DC_ADC0_CLOCK_INIT_COMPLETE); } -void ADC0_init(void) -{ +void ADC0_init(void) { DBGC(DC_ADC0_INIT_BEGIN); - //MCU - PORT->Group[1].DIRCLR.reg = 1 << 0; //PB00 as input 5V - PORT->Group[1].DIRCLR.reg = 1 << 1; //PB01 as input CON2 - PORT->Group[1].DIRCLR.reg = 1 << 2; //PB02 as input CON1 - PORT->Group[1].PMUX[0].bit.PMUXE = 1; //PB00 mux select B ADC 5V - PORT->Group[1].PMUX[0].bit.PMUXO = 1; //PB01 mux select B ADC CON2 - PORT->Group[1].PMUX[1].bit.PMUXE = 1; //PB02 mux select B ADC CON1 - PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; //PB01 mux ADC Enable 5V - PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; //PB01 mux ADC Enable CON2 - PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; //PB02 mux ADC Enable CON1 - - //ADC + // MCU + PORT->Group[1].DIRCLR.reg = 1 << 0; // PB00 as input 5V + PORT->Group[1].DIRCLR.reg = 1 << 1; // PB01 as input CON2 + PORT->Group[1].DIRCLR.reg = 1 << 2; // PB02 as input CON1 + PORT->Group[1].PMUX[0].bit.PMUXE = 1; // PB00 mux select B ADC 5V + PORT->Group[1].PMUX[0].bit.PMUXO = 1; // PB01 mux select B ADC CON2 + PORT->Group[1].PMUX[1].bit.PMUXE = 1; // PB02 mux select B ADC CON1 + PORT->Group[1].PINCFG[0].bit.PMUXEN = 1; // PB01 mux ADC Enable 5V + PORT->Group[1].PINCFG[1].bit.PMUXEN = 1; // PB01 mux ADC Enable CON2 + PORT->Group[1].PINCFG[2].bit.PMUXEN = 1; // PB02 mux ADC Enable CON1 + + // ADC ADC0->CTRLA.bit.SWRST = 1; - while (ADC0->SYNCBUSY.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_1); } - while (ADC0->CTRLA.bit.SWRST) { DBGC(DC_ADC0_SWRST_SYNCING_2); } - - //Clock divide + while (ADC0->SYNCBUSY.bit.SWRST) { + DBGC(DC_ADC0_SWRST_SYNCING_1); + } + while (ADC0->CTRLA.bit.SWRST) { + DBGC(DC_ADC0_SWRST_SYNCING_2); + } + + // Clock divide ADC0->CTRLA.bit.PRESCALER = ADC_CTRLA_PRESCALER_DIV2_Val; - //Averaging + // Averaging ADC0->AVGCTRL.bit.SAMPLENUM = ADC_AVGCTRL_SAMPLENUM_4_Val; - while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_1); } - if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) ADC0->AVGCTRL.bit.ADJRES = 0; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) ADC0->AVGCTRL.bit.ADJRES = 1; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) ADC0->AVGCTRL.bit.ADJRES = 2; - else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) ADC0->AVGCTRL.bit.ADJRES = 3; - else ADC0->AVGCTRL.bit.ADJRES = 4; - while (ADC0->SYNCBUSY.bit.AVGCTRL) { DBGC(DC_ADC0_AVGCTRL_SYNCING_2); } - - //Settling - ADC0->SAMPCTRL.bit.SAMPLEN = 45; //Sampling Time Length: 1-63, 1 ADC CLK per - while (ADC0->SYNCBUSY.bit.SAMPCTRL) { DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); } - - //Load factory calibration data - ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; - ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; + while (ADC0->SYNCBUSY.bit.AVGCTRL) { + DBGC(DC_ADC0_AVGCTRL_SYNCING_1); + } + if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_1_Val) + ADC0->AVGCTRL.bit.ADJRES = 0; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_2_Val) + ADC0->AVGCTRL.bit.ADJRES = 1; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_4_Val) + ADC0->AVGCTRL.bit.ADJRES = 2; + else if (ADC0->AVGCTRL.bit.SAMPLENUM == ADC_AVGCTRL_SAMPLENUM_8_Val) + ADC0->AVGCTRL.bit.ADJRES = 3; + else + ADC0->AVGCTRL.bit.ADJRES = 4; + while (ADC0->SYNCBUSY.bit.AVGCTRL) { + DBGC(DC_ADC0_AVGCTRL_SYNCING_2); + } + + // Settling + ADC0->SAMPCTRL.bit.SAMPLEN = 45; // Sampling Time Length: 1-63, 1 ADC CLK per + while (ADC0->SYNCBUSY.bit.SAMPCTRL) { + DBGC(DC_ADC0_SAMPCTRL_SYNCING_1); + } + + // Load factory calibration data + ADC0->CALIB.bit.BIASCOMP = ((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR) & ADC0_FUSES_BIASCOMP_Msk) >> ADC0_FUSES_BIASCOMP_Pos; + ADC0->CALIB.bit.BIASR2R = ((*(uint32_t *)ADC0_FUSES_BIASR2R_ADDR) & ADC0_FUSES_BIASR2R_Msk) >> ADC0_FUSES_BIASR2R_Pos; ADC0->CALIB.bit.BIASREFBUF = ((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR) & ADC0_FUSES_BIASREFBUF_Msk) >> ADC0_FUSES_BIASREFBUF_Pos; - //Enable + // Enable ADC0->CTRLA.bit.ENABLE = 1; - while (ADC0->SYNCBUSY.bit.ENABLE) { DBGC(DC_ADC0_ENABLE_SYNCING_1); } + while (ADC0->SYNCBUSY.bit.ENABLE) { + DBGC(DC_ADC0_ENABLE_SYNCING_1); + } DBGC(DC_ADC0_INIT_COMPLETE); } -uint16_t adc_get(uint8_t muxpos) -{ +uint16_t adc_get(uint8_t muxpos) { ADC0->INPUTCTRL.bit.MUXPOS = muxpos; - while (ADC0->SYNCBUSY.bit.INPUTCTRL) {} + while (ADC0->SYNCBUSY.bit.INPUTCTRL) { + } ADC0->SWTRIG.bit.START = 1; - while (ADC0->SYNCBUSY.bit.SWTRIG) {} - while (!ADC0->INTFLAG.bit.RESRDY) {} + while (ADC0->SYNCBUSY.bit.SWTRIG) { + } + while (!ADC0->INTFLAG.bit.RESRDY) { + } return ADC0->RESULT.reg; } - -- cgit v1.2.3